Patents by Inventor Kenji Sasaki

Kenji Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10551204
    Abstract: A route search system including an electronic control unit configured to perform: acquiring estimated weather information, the estimated weather information being information about weather that is estimated in a region where a candidate of a first route from a departure place to a destination place exists; acquiring reference weather information, the reference weather information being decided based on statistical information about weather information in a predetermined behavior range of a user; and searching the first route by preferentially selecting a first road over a second road, and outputting information about the first route, the first road being a road in a first region where the estimated weather information is not worse than the reference weather information, the second road being a road in a second region where the estimated weather information is worse than the reference weather information.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: February 4, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Kenji Sasaki, Yuji Sato, Xin Jin
  • Publication number: 20200035879
    Abstract: A method is provided for fabricating an encapsulated emissive element. Beginning with a growth substrate, a plurality of emissive elements is formed. The growth substrate top surface is conformally coated with an encapsulation material. The encapsulation material may be photoresist, a polymer, a light reflective material, or a light absorbing material. The encapsulant is patterned to form fluidic assembly keys having a profile differing from the emissive element profiles. In one aspect, prior to separating the emissive elements from the handling substrate, a fluidic assembly keel or post is formed on each emissive element bottom surface. In one variation, the emissive elements have a horizontal profile. The fluidic assembly key has horizontal profile differing from the emissive element horizontal profile useful in selectively depositing different types of emissive elements during fluidic assembly.
    Type: Application
    Filed: October 8, 2019
    Publication date: January 30, 2020
    Inventors: Kenji Sasaki, Paul J. Schuele
  • Patent number: 10543486
    Abstract: Microperturbation fluidic assembly systems and methods are provided for the fabrication of emissive panels. The method provides an emissive substrate with a top surface patterned to form an array of wells. A liquid suspension is formed over the emissive substrate top surface, comprising a first liquid and emissive elements. Using an array of micropores, a perturbation medium, which optionally includes emissive elements, is injected into the liquid suspension. The perturbation medium may be the first liquid, a second liquid, or a gas. A laminar flow is created in the liquid suspension along the top surface of the emissive substrate in response to the perturbation medium, and emissive elements are captured in the wells. The ejection of the perturbation medium can also be used to control the thickness of the liquid suspension overlying the top surface of the emissive substrate.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: January 28, 2020
    Assignee: eLux Inc.
    Inventors: Kenji Sasaki, Shu-han Yu, Paul J. Schuele
  • Publication number: 20200028188
    Abstract: A resin film equipped MEA of a power generation cell includes a membrane electrode assembly and a resin film. An inner peripheral end of a first frame shaped sheet of the resin film is positioned outside an outer peripheral end of a cathode, and faces the outer peripheral end of the cathode so as to be separated by a gap. An inner peripheral portion of a second frame shaped sheet is held between the anode and the cathode. A first metal separator facing the first frame shaped sheet is provided with protruding support structure configured to support an inner peripheral portion of the first frame shaped sheet and an outer peripheral portion of the cathode.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 23, 2020
    Inventors: Kenji Sasaki, Yutaka Ebato, Takaaki Shikano, Takashi Kato, Sho Nakajima
  • Publication number: 20200006613
    Abstract: A system and method are provided for repairing an emissive display. Following assembly, the emissive substrate is inspected to determine defective array sites, and defect items are removed using a pick-and-remove process. In one aspect, the emissive substrate includes an array of wells, with emissive elements located in the wells, but not electrically connected to the emissive substrate. If the emissive elements are light emitting diodes (LEDs), then the emissive substrate is exposed to ultraviolet illumination to photoexcite the array of LED, so that LED illumination can be measured to determine defective array sites. The defect items may be determined to be misaligned, mis-located, or non-functional emissive elements, or debris. Subsequent to determining these defect items, the robotic pick-and-remove process is used to remove them. The pick-and-remove process can also be repurposed to populate empty wells with replacement emissive elements.
    Type: Application
    Filed: August 23, 2019
    Publication date: January 2, 2020
    Inventors: Kenji Sasaki, Paul J. Schuele, Kurt Ulmer, Jong-Jan Lee
  • Publication number: 20200006536
    Abstract: A semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor (HBT) includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors through respective overlying conductor filled via openings that overlap in a plan view with a width portion of the bump. The semiconductor device reduces heat resistance in an HBT cell by satisfying two conditions, the first of which is related to specific sizing and positioning of a width portion of the overlying via opening relative to the width portion of the bump, and the second of which is related to positioning the base electrode entirely within a specific region of the width portion of the overlapping overlying via opening.
    Type: Application
    Filed: September 11, 2019
    Publication date: January 2, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kenji SASAKI, Kingo KUROTANI, Takashi KITAHARA, Shigeki KOYA
  • Patent number: 10520769
    Abstract: A multi-color emissive display is presented with printed light modifier structures. A fabrication method provides an emissive substrate with a plurality of wells formed in the emissions substrate top surface, and a plurality of emissive elements populating the wells. The method prints light modifier structures overlying the emissive elements. Some examples of light modifier material include light scattering materials, phosphors, and quantum dots. In one aspect, the emissive substrate wells have a first shape, with sidewalls and a first perimeter. Likewise, the emissive elements have the first shape, with sides and a second perimeter, less than the first perimeter. The light modifier structures fill the space between the emissive element sides and the well sidewalls with light modifier material. If the first shape is circular, the method prints the light modifier structures overlying the emissive elements in the circular shape having a first diameter defined by the well sidewalls.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: December 31, 2019
    Assignee: eLux, Inc.
    Inventors: Kurt Ulmer, Jong-Jan Lee, Kenji Sasaki, Paul J. Schuele
  • Patent number: 10516084
    Abstract: A method is provided for fabricating an encapsulated emissive element. Beginning with a growth substrate, a plurality of emissive elements is formed. The growth substrate top surface is conformally coated with an encapsulation material. The encapsulation material may be photoresist, a polymer, a light reflective material, or a light absorbing material. The encapsulant is patterned to form fluidic assembly keys having a profile differing from the emissive element profiles. In one aspect, prior to separating the emissive elements from the handling substrate, a fluidic assembly keel or post is formed on each emissive element bottom surface. In one variation, the emissive elements have a horizontal profile. The fluidic assembly key has horizontal profile differing from the emissive element horizontal profile useful in selectively depositing different types of emissive elements during fluidic assembly.
    Type: Grant
    Filed: September 8, 2018
    Date of Patent: December 24, 2019
    Assignee: eLux, Inc.
    Inventors: Kenji Sasaki, Paul J. Schuele
  • Publication number: 20190355708
    Abstract: A hybrid light emitting diode (LED) display and fabrication method are provided. The method forms a stack of thin-film layers overlying a top surface of a substrate. The stack includes an LED control matrix and a plurality of pixels. Each pixel is made up of a first subpixel enabled using an inorganic micro LED (uLED), a second subpixel enabled using an organic LED (OLED), and a third subpixel enabled using an OLED. The first subpixel emits a blue color light, the second subpixel emits a red color light, and the third subpixel emits a green color light. In one aspect, the stack includes a plurality of wells in a top surface of the stack, populated by the LEDs. The uLEDs may be configured vertical structures with top and bottom electrical contacts, or surface mount top surface contacts. The uLEDs may also include posts for fluidic assembly orientation.
    Type: Application
    Filed: July 11, 2019
    Publication date: November 21, 2019
    Inventors: Kenji Sasaki, Paul J. Schuele, Kurt Ulmer, Jong-Jan Lee
  • Patent number: 10476439
    Abstract: A power amplifier circuit includes a first amplifier transistor and a bias circuit. The first amplifier transistor amplifies a first signal and outputs a second signal. The bias circuit supplies a bias voltage or a bias current to the first amplifier transistor. The first amplifier transistor includes plural unit transistors disposed in a substantially rectangular region. The bias circuit includes first and second bias transistors and first and second voltage supply circuits. The first and second bias transistors respectively supply first and second bias voltages or first and second bias currents to the bases of unit transistors of first and second groups. The first and second voltage supply circuits respectively supply first and second voltages to the bases of the first and second bias transistors. The first and second voltages are decreased in accordance with a temperature increase. The second voltage supply circuit is disposed within the substantially rectangular region.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 12, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kenji Sasaki
  • Patent number: 10468335
    Abstract: Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor includes: a collector layer that has a long-side direction and a short-side direction in a plan view, in which the short-side direction is parallel to crystal orientation [011], a cross-section perpendicular to the short-side direction has an inverted mesa shape, and a cross-section perpendicular to the long-side direction has a forward mesa shape; a base layer that is formed on the collector layer; a base electrode that is formed on the base layer; and a base line that is connected to the base electrode and that is drawn out from an end in the short-side direction of the collector layer to the outside of the collector layer in a plan view.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: November 5, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kenji Sasaki
  • Publication number: 20190319015
    Abstract: Planar surface mount (SM) micro light emitting diodes (?LEDs) are presented. The fabrication method provides a MOCVD LED structure with a stack including a first doped semiconductor in a first plane, a MQW layer overlying the first doped semiconductor in a second plane, and a second doped semiconductor overlying the MQW layer in a third plane. An electrical insulator is conformally deposited over the etched stack in a fourth plane, and etched to expose the second doped semiconductor, creating a first via. Etching exposes the first doped semiconductor, creating a second via. A first electrode is connected to the second doped semiconductor through the first via, and has a substrate interface surface in a fifth plane with an average planarity tolerance of less than 10 nanometers. A second electrode is connected to the first doped semiconductor through the second via, and has a substrate interface surface in the fifth plane.
    Type: Application
    Filed: May 8, 2019
    Publication date: October 17, 2019
    Inventors: Paul J. Schuele, Changqing Zhan, Kenji Sasaki, Kurt Ulmer, Jong-Jan Lee
  • Publication number: 20190319163
    Abstract: Planar surface mount (SM) micro light emitting diodes (?LEDs) are presented. The fabrication method provides a MOCVD LED structure with a stack including a first doped semiconductor in a first plane, a MQW layer overlying the first doped semiconductor in a second plane, and a second doped semiconductor overlying the MQW layer in a third plane. An electrical insulator is conformally deposited over the etched stack in a fourth plane, and etched to expose the second doped semiconductor, creating a first via. Etching exposes the first doped semiconductor, creating a second via. A first electrode is connected to the second doped semiconductor through the first via, and has a substrate interface surface in a fifth plane with an average planarity tolerance of less than 10 nanometers. A second electrode is connected to the first doped semiconductor through the second via, and has a substrate interface surface in the fifth plane.
    Type: Application
    Filed: May 8, 2019
    Publication date: October 17, 2019
    Inventors: Paul J. Schuele, Changqing Zhan, Kenji Sasaki, Kurt Ulmer, Jong-Jan Lee
  • Patent number: 10446728
    Abstract: A system and method are provided for repairing an emissive display. Following assembly, the emissive substrate is inspected to determine defective array sites, and defect items are removed using a pick-and-remove process. In one aspect, the emissive substrate includes an array of wells, with emissive elements located in the wells, but not electrically connected to the emissive substrate. If the emissive elements are light emitting diodes (LEDs), then the emissive substrate is exposed to ultraviolet illumination to photoexcite the array of LED, so that LED illumination can be measured to determine defective array sites. The defect items may be determined to be misaligned, mis-located, or non-functional emissive elements, or debris. Subsequent to determining these defect items, the robotic pick-and-remove process is used to remove them. The pick-and-remove process can also be repurposed to populate empty wells with replacement emissive elements.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: October 15, 2019
    Assignee: eLux, Inc.
    Inventors: Kenji Sasaki, Paul J. Schuele, Kurt Ulmer, Jong-Jan Lee
  • Publication number: 20190312554
    Abstract: A power amplifier circuit is capable of restraining uneven temperature distribution among a plurality of unit transistors while restraining the deterioration of the characteristics of the power amplifier circuit. The power amplifier circuit includes: a first transistor group which includes a plurality of unit transistors and which amplifies an input signal and outputs an amplified signal; a bias circuit which supplies a bias current or a bias voltage to a base or a gate of each unit transistor of the first transistor group; a plurality of first resistive elements, each of which is connected between the base or the gate of each unit transistor of the first transistor group and an output of the bias circuit; and a plurality of second resistive elements, each of which is connected between an emitter or a source of each unit transistor of the first transistor group and a reference potential.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Inventors: Toshiki MATSUI, Kenji SASAKI, Fumio HARIMA
  • Publication number: 20190293972
    Abstract: A dielectric thin film-applied substrate capable of suppressing occurrence of cracks even when the film thickness of the lithium niobate film is made, e.g., equal to or larger than 1 ?m. The dielectric thin film-applied substrate includes a single crystal substrate and a dielectric thin film which is made of c-axis oriented lithium niobate and epitaxially formed on a main surface of the single crystal substrate. The dielectric thin film has a twin crystal structure including a first and crystals existing at a position obtained by rotating the first crystal 180° centered on the c-axis. In pole figure measurement by an X-ray diffraction method, the ratio between a first diffraction intensity corresponding to the first crystal and a second diffraction intensity corresponding to the second crystal is equal to or higher than 0.5 and equal to or lower than 2.0.
    Type: Application
    Filed: July 14, 2017
    Publication date: September 26, 2019
    Applicant: TDK CORPORATION
    Inventors: Kenji SASAKI, Shinji IWATSUKA
  • Patent number: 10418527
    Abstract: Fluidic assembly methods are presented for the fabrication of emissive displays. An emissive substrate is provided with a top surface, and a first plurality of wells formed in the top surface. Each well has a bottom surface with a first electrical interface. Also provided is a liquid suspension of emissive elements. The suspension is flowed across the emissive substrate and the emissive elements are captured in the wells. As a result of annealing the emissive substrate, electrical connections are made between each emissive element to the first electrical interface of a corresponding well. A eutectic solder interface metal on either the substrate or the emissive element is desirable as well as the use of a fluxing agent prior to thermal anneal. The emissive element may be a surface mount light emitting diode (SMLED) with two electrical contacts on its top surface (adjacent to the bottom surfaces of the wells).
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: September 17, 2019
    Assignee: eLux, Inc.
    Inventors: Kenji Sasaki, Paul J. Schuele, Kurt Ulmer, Jong-Jan Lee
  • Publication number: 20190273269
    Abstract: A frame equipped membrane electrode assembly includes a membrane electrode assembly and a frame member. The frame member includes a first frame shaped sheet and a second frame shaped sheet. An inner peripheral portion of the first frame shaped sheet is joined to an outer peripheral portion of the membrane electrode assembly. The inner peripheral portion of the first frame shaped sheet is positioned between an outer peripheral portion of an anode and an outer peripheral portion of a cathode. An inner end of the second frame shaped sheet is positioned outside an outer end of the anode over the entire periphery. The outer end of the cathode is positioned outside the inner end of the second frame shaped sheet over the entire periphery.
    Type: Application
    Filed: March 2, 2018
    Publication date: September 5, 2019
    Inventors: Yutaka EBATO, Kentaro ISHIDA, Kenji SASAKI, Hiroyuki TANAKA, Takaaki SHIKANO
  • Publication number: 20190271897
    Abstract: Disclosed herein is an optical waveguide element that includes a substrate and a waveguide layer formed on the substrate and comprising lithium niobate. The waveguide layer has a slab part having a predetermined thickness and a ridge part protruding from the slab part. The maximum thickness of the slab part is 0.05 times or more and less than 0.4 times a wavelength of a light propagating in the ridge part.
    Type: Application
    Filed: May 13, 2019
    Publication date: September 5, 2019
    Applicant: TDK Corporation
    Inventors: Shinji IWATSUKA, Kenji SASAKI, Satoshi SHIRAI
  • Patent number: 10394180
    Abstract: A cleaning blade 1 includes an elastic body 11 that is a molded body of a rubber base material, and which has at least a surface treatment layer 12 in a portion of the elastic body 11, the portion coming into contact with an object to be contacted. The surface treatment layer 12 is formed by impregnating a surface portion of the elastic body 11 with a surface treatment liquid, which contains an isocyanate compound and an organic solvent, and curing the surface treatment liquid; the surface treatment layer 12 has an elastic modulus of 95 MPa or less; the elastic body 11 has an elastic modulus of from 20 MPa to 60 MPa (inclusive); and the difference between the elastic modulus of the surface treatment layer 12 and the elastic modulus of the elastic body 11 is 1 MPa or more.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: August 27, 2019
    Assignees: NOK CORPORATION, SYNZTEC CO., LTD.
    Inventors: Syo Kawabata, Kenji Sasaki, Yasushi Sugiyama, Hiroaki Kaneda, Natsumi Kimura, Katsuya Shimotsuma, Koji Nishiguchi, Shuji Abe, Hidetomo Mukai