Patents by Inventor Kenji Tsuchida

Kenji Tsuchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10924072
    Abstract: A power amplification circuit includes an amplification transistor, a variable voltage power supply that supplies a variable voltage to a collector of the amplification transistor, a bias circuit that has a constant current amplification transistor outputting a DC bias current to a base of the amplifier transistor, and a current limiting circuit that limits the DC bias current. The current limiting circuit includes a current limiting transistor, a resistor element connected to a collector of the current limiting transistor and the variable voltage power supply, and a resistor element connected to a base of the current limiting transistor and a base of the constant current amplifying transistor.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: February 16, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kenji Tahara, Kenichi Shimamoto, Shigeru Tsuchida, Mitsunori Samata, Yoshiaki Sukemori
  • Publication number: 20210025428
    Abstract: Provided is a fiber-reinforced resin bolt having a strength higher than that of a conventional fiber-reinforced resin bolt. A fiber-reinforced resin bolt 1 formed by a winding step of winding a CFRP resin tape 14, which is formed in a band shape by integrating CFRP 12 with a thermosetting resin in such a manner that the CFRP 12 is oriented in a longitudinal direction, so that the CFRP 12 is arranged concentrically around a winding axis, thereby forming a CFRP resin tape layer 10; and a curing step of placing the CFRP resin tape layer 10 formed by the winding step in a die 40 whose inner wall surface is formed with a screw shape, pressurizing the die 40 in which the CFRP resin tape layer 10 is placed from one direction of the winding axis to the other, and heating the die 40 with a heater 82, thereby curing the resin containing the CFRP resin tape layer 10.
    Type: Application
    Filed: January 11, 2019
    Publication date: January 28, 2021
    Inventors: Kenji TSUCHIDA, Yasuhiro FURUTA
  • Patent number: 10820431
    Abstract: The ventilation efficiency is improved while exposure of a part disposed at the inner side of an electronic apparatus is suppressed. An electronic apparatus has a first shielding portion and a second shielding portion disposed behind a circuit board. The first shielding portion and the second shielding portion are juxtaposed in an upward and downward direction. Further, the first shielding portion and the second shielding portion are disposed in a displaced relationship from each other in a forward and rearward direction, and a first exhaust port is provided between the first shielding portion and the second shielding portion.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: October 27, 2020
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Kenji Hirose, Shinya Tsuchida, Yasuhiro Ootori
  • Patent number: 10771672
    Abstract: The present invention provides a detachable-head-type camera which, when a camera head unit is exchanged, can perform correction processing with a unique value corresponding to a camera head unit after the exchange, and provides a work machine including the detachable-head-type camera. Camera head unit of detachable-head-type camera is detachably connected to image data generation section via dedicated cable. In non-volatile memory of camera head unit, unique value corresponding to the characteristics unique to at least one of imaging element or lens is stored. Unique value is used for correction processing of image data performed by at least one of image data generation section or image processing unit.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: September 8, 2020
    Assignee: FUJI CORPORATION
    Inventors: Kosuke Tsuchida, Nobuo Nagasaka, Hidekazu Kanai, Kenji Watanabe
  • Patent number: 10746893
    Abstract: A proximity sensor that outputs presence or absence of a detection object or a position of the detection object as a detection result includes: a detection part configured to include a detection coil and a capacitor; an oscillation circuit configured to excite the detection part; an analog/digital conversion circuit configured to detect a signal change occurring in the detection part and output a digital signal indicating the detected signal change; a temperature detection part configured to detect a temperature inside a casing of the proximity sensor; a storage part configured to store a characteristic parameter unique to the proximity sensor in advance; a control calculation part configured to process a digital signal from the analog/digital conversion circuit to calculate a signal indicating a distance to the detection object, compensate the calculated signal using the characteristics parameter stored in the storage part, and output the compensated signal as the detection result.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 18, 2020
    Assignee: OMRON Corporation
    Inventors: Ryota Hasegawa, Hiroyuki Tsuchida, Kazuaki Miyamoto, Yusuke Hayashi, Kenji Matsuoka
  • Patent number: 10658063
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a read circuit, a correcting circuit and a write circuit. The read circuit is configured to read first data from the memory cell by receiving a first command. The correcting circuit is configured to generate second data by correcting an error included in the first data. The write circuit is configured to write the second data to the memory cell in response to receiving a second command.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 19, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiromi Noro, Kenji Tsuchida
  • Patent number: 10553520
    Abstract: A leaf spring is disposed between a circuit board and a upper shield. The leaf spring biases a heat sink toward the circuit board through a connecting member. The leaf spring is not electrically connected to the upper shield. According to this structure, an integrated circuit and the heat sink can be contacted with each other with certainty. Further, generation of unnecessary radiation can be suppressed effectively.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: February 4, 2020
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Hitomi Iizuka, Hiroaki Tsurumi, Shinya Tsuchida, Kenji Hirose, Yuta Tamaki
  • Patent number: 10508930
    Abstract: A method of manufacturing a proximity sensor and a manufacturing system for the proximity sensor capable of improving detection precision or expanding a detectable range are provided. A method of manufacturing a proximity sensor outputting presence or absence of a detection object or a position of the detection object as a detection result is provided. The manufacturing method includes: disposing the proximity sensor in a temperature-changeable environment; setting an environment of the proximity sensor to a plurality of different temperatures respectively and storing temperature detected by the temperature detection part of the proximity sensor in association with the detection result output by the control calculation part at each temperature; determining a characteristic parameter unique to a target proximity sensor based on the stored temperature and detection result; and setting the determined characteristic parameter for the target proximity sensor.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: December 17, 2019
    Assignee: OMRON Corporation
    Inventors: Ryota Hasegawa, Hiroyuki Tsuchida, Kazuaki Miyamoto, Yusuke Hayashi, Kenji Matsuoka
  • Patent number: 10446192
    Abstract: An electronic apparatus includes a plurality of parts, a frame having an outer periphery surrounding the plurality of parts and formed from resin, a circuit board disposed at one side in a first direction with respect to the plurality of parts, a chassis disposed at the one side in the first direction with respect to the plurality of parts, and formed from metal, and a metal plate disposed at the other side in the first direction with respect to at least one of the plurality of parts and attached to the frame.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: October 15, 2019
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Kenji Hirose, Kazuto Nakagawa, Shinya Tsuchida, Yasuhiro Ootori
  • Publication number: 20190305736
    Abstract: A power amplification circuit includes an amplification transistor, a variable voltage power supply that supplies a variable voltage to a collector of the amplification transistor, a bias circuit that has a constant current amplification transistor outputting a DC bias current to a base of the amplifier transistor, and a current limiting circuit that limits the DC bias current. The current limiting circuit includes a current limiting transistor, a resistor element connected to a collector of the current limiting transistor and the variable voltage power supply, and a resistor element connected to a base of the current limiting transistor and a base of the constant current amplifying transistor.
    Type: Application
    Filed: March 8, 2019
    Publication date: October 3, 2019
    Inventors: Kenji TAHARA, Kenichi SHIMAMOTO, Shigeru TSUCHIDA, Mitsunori SAMATA, Yoshiaki SUKEMORI
  • Publication number: 20190246017
    Abstract: The present invention provides a detachable-head-type camera which, when a camera head unit is exchanged, can perform correction processing with a unique value corresponding to a camera head unit after the exchange, and provides a work machine including the detachable-head-type camera. Camera head unit of detachable-head-type camera is detachably connected to image data generation section via dedicated cable. In non-volatile memory of camera head unit, unique value corresponding to the characteristics unique to at least one of imaging element or lens is stored. Unique value is used for correction processing of image data performed by at least one of image data generation section or image processing unit.
    Type: Application
    Filed: August 2, 2016
    Publication date: August 8, 2019
    Applicant: FUJI CORPORATION
    Inventors: Kosuke TSUCHIDA, Nobuo NAGASAKA, Hidekazu KANAI, Kenji WATANABE
  • Publication number: 20190130986
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a read circuit, a correcting circuit and a write circuit. The read circuit is configured to read first data from the memory cell by receiving a first command. The correcting circuit is configured to generate second data by correcting an error included in the first data. The write circuit is configured to write the second data to the memory cell in response to receiving a second command.
    Type: Application
    Filed: September 6, 2018
    Publication date: May 2, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Hiromi NORO, Kenji TSUCHIDA
  • Patent number: 9997216
    Abstract: A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: June 12, 2018
    Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.
    Inventors: Yutaka Shirai, Naoki Shimizu, Kenji Tsuchida, Yoji Watanabe, Ji Hyae Bae, Yong Ho Kim
  • Publication number: 20170169869
    Abstract: A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 15, 2017
    Applicants: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.
    Inventors: Yutaka SHIRAI, Naoki SHIMIZU, Kenji TSUCHIDA, Yoji WATANABE, Ji Hyae BAE, Yong Ho KIM
  • Patent number: 9613671
    Abstract: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: April 4, 2017
    Assignees: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.
    Inventors: Yutaka Shirai, Naoki Shimizu, Kenji Tsuchida, Yoji Watanabe, Ji Hyae Bae, Yong Ho Kim
  • Publication number: 20150228320
    Abstract: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.
    Type: Application
    Filed: April 21, 2015
    Publication date: August 13, 2015
    Inventors: Yutaka SHIRAI, Naoki SHIMIZU, Kenji TSUCHIDA, Yoji WATANABE, Ji Hyae BAE, Yong Ho KIM
  • Patent number: 9042198
    Abstract: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: May 26, 2015
    Inventors: Yutaka Shirai, Naoki Shimizu, Kenji Tsuchida, Yoji Watanabe, Ji Hyae Bae, Yong Ho Kim
  • Publication number: 20140286115
    Abstract: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.
    Type: Application
    Filed: September 6, 2013
    Publication date: September 25, 2014
    Inventors: Yutaka SHIRAI, Naoki SHIMIZU, Kenji TSUCHIDA, Yoji WATANABE, Ji Hyae BAE, Yong Ho KIM
  • Patent number: RE46702
    Abstract: A memory according to an embodiment includes bit lines, word lines, source lines, magnetic tunnel junction elements and transistors that are serially connected between the bit lines and the source lines, respectively, and a sense amplifier that detects data stored in the magnetic tunnel junction elements. The semiconductor storage device includes multiplexers between the bit lines and the sense amplifier in order to select one of the bit lines to be connected to the sense amplifier, and write amplifiers that are located corresponding to memory cell blocks each of which includes memory cells each including the magnetic tunnel junction element and the transistor and are connected to the bit lines or connected via the multiplexers to the bit lines. To write data, the sense amplifier applies a write voltage to the bit lines and then the write amplifiers hold the write voltage.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: February 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsuhiko Hoya, Kenji Tsuchida
  • Patent number: RE46920
    Abstract: According to one embodiment, a semiconductor memory device includes a variable resistance element configured to store data “0” and data “1” in accordance with a change in resistance value, a current generator configured to generate a reference current for determining data of the variable resistance element, and having an admittance middle at a level in between an admittance of a variable resistance element storing data “0” and an admittance of a variable resistance element storing data “1”, and a sense amplifier includes a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: June 26, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Katsuyuki Fujita, Kenji Tsuchida