Abstract: A memory cell of a magnetic memory device has an MTJ element and one end of the memory cell is selectively electrically connected to a ground potential line. A first bit line is electrically connected to the other end of the memory cell. A sense amplifier amplifies a difference in potential between the first bit line and a second bit line complementary to the first bit line so that the difference is equal to or larger than a difference between an internal power potential and a ground potential. A connection circuit disconnects the MTJ element from an electric connection between the ground potential line and the sense amplifier.

Abstract: A semiconductor integrated circuit device has a semiconductor substrate comprising a first region extending along the edge and a second region surrounded by the first region. Memory cell arrays are provided in the second region, and comprising a plurality of cells having an MTJ element. Gate transistors are provided in the first region, and have a current path having a first terminal connected with a bit line, which is a signal read path from the cells, and a second terminal opposite to the first terminal. Data buses are connected with the same number of the second terminals. A connection control circuit is provided in the second region, and connects selected two of the data buses to first and second output terminals, respectively. An amplifier circuit is provided in the first region, and amplifies a potential difference in accordance with signals outputted from the first and second output terminals.

Abstract: A memory cell array is of a hierarchical bit line scheme in which cross-point memory cells that exhibit a magnetoresistive effect are laid out in a matrix, and a read bit line to be used in a data read mode is constituted by a main bit line and a sub bit line. A column select circuit selects a main bit line and connects it to a sense amplifier. A row select circuit selects a word line for each cell unit, and in read operation, sets, in a floating state, word lines to which unselected memory cells connected to the sub bit line to which a selected memory cell is connected are connected, and sets the remaining word lines connected to sub bit lines which do not include the selected memory cell to a potential substantially equal to the main bit line.

Abstract: An MRAM that employs a constant current write method includes a constant current circuit for a write, which is connected to a first power supply, and switch circuits which are connected to the constant current circuit to selectively drive a write line. In the MRAM, before the write current application timing, the node at one of the terminals of each of the switch circuits is short-circuited to the power supply to which the constant current source is connected.

Abstract: An MRAM that employs a constant current write method includes a constant current circuit for a write, which is connected to a first power supply, and switch circuits which are connected to the constant current circuit to selectively drive a write line. In the MRAM, before the write current application timing, the node at one of the terminals of each of the switch circuits is short-circuited to the power supply to which the constant current source is connected.

Abstract: An MRAM has an internal test circuit. This test circuit detects a bit in a memory cell array, which has a shift in write characteristics, as a defective bit by using a method of applying a one-axis write current along an axis of hard magnetization.

Abstract: A memory cell comprises a magneto-resistive element of which electrical resistance value varies with magnetism. A sub-bit line is connected to one end of the memory cell. A main-bit line is connected to the sub-bit line via a first selection circuit. A sense-amplifier is connected to the main-bit line via a second selection circuit. A wiring line is connected to the other end of the memory cell and arranged in a first direction. A first operation circuit is connected to one end of the wiring line via a third selection circuit. A second operation circuit is connected to the other end of the wiring line. A word line passes over an intersection between the memory cell and the wiring line and is arranged in a second direction perpendicular to the first direction.

Abstract: A memory cell array is of a hierarchical bit line scheme in which cross-point memory cells that exhibit a magnetoresistive effect are laid out in a matrix, and a read bit line to be used in a data read mode is constituted by a main bit line and a sub bit line. A column select circuit selects a main bit line and connects it to a sense amplifier. A row select circuit selects a word line for each cell unit, and in read operation, sets, in a floating state, word lines to which unselected memory cells connected to the sub bit line to which a selected memory cell is connected are connected, and sets the remaining word lines connected to sub bit lines which do not include the selected memory cell to a potential substantially equal to the main bit line.

Abstract: Reference cells are provided in a memory cell array. When the data is read, the data in the reference cells are inverted, thereby preventing the data in the selected cell from changing. This makes it possible to decrease the number of write operations and realize a high-speed read operation and lower power consumption.

Abstract: Reference cells are provided in a memory cell array. When the data is read, the data in the reference cells are inverted, thereby preventing the data in the selected cell from changing. This makes it possible to decrease the number of write operations and realize a high-speed read operation and lower power consumption.

Abstract: A memory cell comprises a magneto-resistive element of which electrical resistance value varies with magnetism. A sub-bit line is connected to one end of the memory cell. A main-bit line is connected to the sub-bit line via a first selection circuit. A sense-amplifier is connected to the main-bit line via a second selection circuit. A wiring line is connected to the other end of the memory cell and arranged in a first direction. A first operation circuit is connected to one end of the wiring line via a third selection circuit. A second operation circuit is connected to the other end of the wiring line. A word line passes over an intersection between the memory cell and the wiring line and is arranged in a second direction perpendicular to the first direction.

Abstract: After data readout, in equalizing a complementary pair of bit lines one of which has been overdriven with an overdrive voltage, excessive charges on the overdriven bit line are discharged by a discharge circuit. By adjusting the discharge period of the discharge circuit, the potential to which the bit lines are equalized is adjusted.

Abstract: A semiconductor integrated circuit device comprises a plurality of MIS transistors, and an integrated circuit unit including logic gate circuits configured by a combination of the plurality of MIS transistors. Each of the MIS transistors has a gate including a circuit element represented by an equivalent circuit in which a capacitance and resistance are parallel-connected.

Abstract: A semiconductor memory device includes a bit line, a memory cell coupled to the bit line and a word line coupled to the memory cell. A first time between receiving a write command for a write operation in order to write data to the memory cell and the beginning of the write operation is different from a second time between receiving a refresh command for a refresh operation in order to refresh data stored in the memory cell and beginning the write operation.

Abstract: A semiconductor memory device is disclosed, in which a first word drive line control circuit which supplies a word drive voltage corresponding to the decode output of the decoding circuit to the first word drive line, and has a first reset circuit which resets the first word drive line to a first potential when a first control signal is activated and a second reset circuit which resets the first word drive line to a second potential when a second control signal is activated, and a two-stage reset control circuit which controls changeover from the activated state of the first control signal to the activated state of the second control signal on the basis of the potential of the first word drive line to change the potential of the first word drive line in two stages.

Abstract: One (first level shift circuit) of first and second level shift circuits is provided in a local word-drive-line driving circuit located near memory cell arrays. The second level shift circuit is provided in a global word-drive-line driving circuit located remote from the memory cell arrays.

Abstract: A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line and a word line coupled to the memory cell. A first time between the receiving of a read command for a read operation in order to read data from the memory cell and the beginning of the read operation is different from a second time between the receiving of a write command for a write operation in order to write data to the memory cell and the beginning of the write operation.

Abstract: After data readout, in equalizing a complementary pair of bit lines one of which has been overdriven with an overdrive voltage, excessive charges on the overdriven bit line are discharged by a discharge circuit. By adjusting the discharge period of the discharge circuit, the potential to which the bit lines are equalized is adjusted.

Abstract: A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line a word line coupled to the memory cell. A first time between the receiving of a read command for a read operation in order to read data from the memory cell and the beginning of read operation is different from a second time between the receiving of a write command for a write operation in order to write data to the memory cell and the beginning of the write operation.

Abstract: A clock signal generator circuit comprises an off-chip driver, a first clock control circuit for outputting a first internal clock signal Tu synchronizing with an external clock signal CK, a second clock control circuit for outputting a second internal clock signal Td 180° out-of-phase with the external clock signal CK, a third clock control circuit for outputting a third internal clock signal aTx1 synchronizing with the first clock signal Tu and advanced in phase by at least the signal delay time in the off-chip driver, a fourth clock control circuit for outputting a fourth internal clock signal aTx2 synchronizing with the second clock signal Td and advanced in phase by at least the signal delay time in the off-chip driver, an OR circuit to which the third and fourth internal clock signals aTx1, aTx2 are inputted and which outputs a fifth internal clock signal aTx, and a fifth clock control circuit for outputting a sixth internal clock signal Tx which is in synchronization with the fifth internal clock s