Patents by Inventor Kenji Yamagata

Kenji Yamagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040259328
    Abstract: An SOI substrate which has a thick SOI layer is first prepared. Then, the SOI layer is thinned to a target film thickness using as a unit a predetermined thickness not more than that of one lattice. This thinning is performed by repeating a unit thinning step which includes an oxidation step of oxidizing the surface of the SOI layer by the predetermined thickness not more than that of one lattice and a removal step of selectively removing silicon oxide formed by the oxidation. The SOI layer of the SOI substrate is chemically etched by supplying a chemical solution to the SOI layer, and the film thickness of the etched SOI layer is measured. When the measured film thickness of the SOI layer has a predetermined value, a process of chemically etching the SOI layer ends.
    Type: Application
    Filed: May 10, 2004
    Publication date: December 23, 2004
    Applicant: Canon Kabushiki Kaisha
    Inventors: Masataka Ito, Kenji Yamagata, Yasuo Kakizaki, Kazuhito Takanashi, Hiroshi Miyabayashi, Ryuji Moriwaki, Takashi Tsuboi
  • Publication number: 20040169011
    Abstract: An object of this invention is to suppress the amount of etchant used. A liquid etchant is stored in an etchant vessel, and vaporized by a vaporization unit. A fragile layer such as a porous layer is selectively etched with the vaporized etchant.
    Type: Application
    Filed: January 12, 2004
    Publication date: September 2, 2004
    Applicant: Canon Kabushiki Kaisha
    Inventors: Kazuhito Takanashi, Kenji Yamagata, Kiyofumi Sakaguchi, Kazutaka Yanagita, Takashi Sugai, Takashi Tsuboi
  • Publication number: 20040171231
    Abstract: A unit which overlays first and second substrates, after the surfaces of the first and second substrates are cleaned and/or activated, is accommodated in a chamber, and the interior of the chamber is isolated from an outer space. In the chamber isolated from the outer space, the state of the surfaces of the first and second substrates is measured. The surfaces of the first and second substrates are cleaned on the basis of the measurement result. After that, the first and second substrates are overlaid.
    Type: Application
    Filed: February 27, 2004
    Publication date: September 2, 2004
    Inventors: Kazutaka Yanagita, Kenji Yamagata
  • Publication number: 20040152319
    Abstract: Even when the substrate size increases, the substrate is processed (etched) uniformly. An ultrasonic oscillator (103) is arranged under an etching container (101). A substrate (120) is horizontally arranged in the etching container (101). Accordingly, the substrate (120) is arranged while making a surface face the ultrasonic oscillator (103). The substrate (120) is etched while being rotated by a rotating mechanism (130).
    Type: Application
    Filed: December 12, 2003
    Publication date: August 5, 2004
    Applicant: Canon Kabushiki Kaisha
    Inventors: Kenji Yamagata, Kiyofumi Sakaguchi, Kazutaka Yanagita, Takashi Sugai, Kazuhito Takanashi
  • Publication number: 20040124088
    Abstract: Openings are formed at the bottom of an anodizing container. A shower-type current path forming mechanism is arranged at the lower portion of the anodizing container. The mechanism has a pressure vessel. A shower head is arranged at the upper portion of the pressure vessel. A conductive solution in a shower form is injected or discharged from the shower head to form a liquid electrode under the lower surface of a substrate. Accordingly, a current flows between a cathode and an anode to anodize the substrate. The apparatus also has a mechanism which makes a chemical solution overflow from a chemical solution container to form a flow of the chemical solution near the lower surface of the substrate.
    Type: Application
    Filed: December 17, 2003
    Publication date: July 1, 2004
    Applicant: Canon Kabushiki Kaisha
    Inventors: Takashi Tsuboi, Kenji Yamagata, Kiyofumi Sakaguchi, Kazutaka Yanagita, Takashi Sugai, Kazuhito Takanashi
  • Patent number: 6706618
    Abstract: The spaces in chuck grooves 3a and 3b are evacuated to chuck the entire surface of a wafer 1 to the chuck surface of a wafer support table 3 and curve the wafer 1. A wafer 2 is horizontally opposed to the wafer 1, and the center of the wafer 2 is pressed by a press pin 6a. The centers of the two wafers 1 and 2 are contacted, and the contact portion gradually spreads to the vicinity of the periphery of a central portion 3c and takes a substantially circular shape. After that, the chuck by the chuck grooves 3a is stopped. Consequently, the wafer 1 flattens, and the entire surfaces of the wafers 1 and 2 are contacted.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: March 16, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toru Takisawa, Takao Yonehara, Kenji Yamagata
  • Patent number: 6653209
    Abstract: To decrease the thickness of a silicon thin film to a desired value without deterioration of the quality thereof while avoiding the surface roughness due to speed increasing oxidation of crystal defect portions occurring when conducting the conventional sacrificial oxidation, effect of dust particles, etc. and also avoiding deterioration of high pressure resistance of the oxide film associated with the surface roughness. A silicon ultrathin film SOI layer is produced in the following two steps: preparing a SOI wafer having a silicon thin film, which exhibits less precipitation of oxygen, thereon by the SIMOX method or the semiconductor bonding method, and cleaning the SOI wafer with an alkali solution such as SC1 and TMAH, so as to utilize the etching action of the aqueous cleaner.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: November 25, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenji Yamagata
  • Publication number: 20030203547
    Abstract: A process for producing a semiconductor article is provided which comprises the steps of bonding a film onto a substrate having a porous semiconductor layer, and separating the film from the substrate at the porous semiconductor layer by applying a force to the film in a peeling direction.
    Type: Application
    Filed: January 9, 2003
    Publication date: October 30, 2003
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara, Shoji Nishida, Kenji Yamagata
  • Publication number: 20030121773
    Abstract: This invention is to reduce the influence of a gas generated by an anodizing reaction. A silicon substrate (101) to be processed is horizontally held. A negative electrode (129) is arranged on the upper side of the silicon substrate (101), and a positive electrode (114) is brought into contact with the lower surface of the silicon substrate (101). The space between the negative electrode (129) and the silicon substrate (101) is filled with an HF solution (132). The negative electrode (129) has a number of degassing holes (130) to prevent a gas generated by the anodizing reaction from staying on the lower side of the negative electrode (129).
    Type: Application
    Filed: February 19, 2003
    Publication date: July 3, 2003
    Inventors: Satoshi Matsumura, Kenji Yamagata
  • Patent number: 6547938
    Abstract: This invention is to reduce the influence of a gas generated by an anodizing reaction. A silicon substrate (101) to be processed is horizontally held. A negative electrode (129) is arranged on the upper side of the silicon substrate (101), and a positive electrode (114) is brought into contact with the lower surface of the silicon substrate (101). The space between the negative electrode (129) and the silicon substrate (101) is filled with an HF solution (132). The negative electrode (129) has a number of degassing holes (130) to prevent a gas generated by the anodizing reaction from staying on the lower side of the negative electrode (129).
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: April 15, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoshi Matsumura, Kenji Yamagata
  • Patent number: 6534382
    Abstract: A process for producing a semiconductor article is provided which comprises the steps of bonding a film onto a substrate having a porous semiconductor layer, and separating the film from the substrate at the porous semiconductor layer by applying a force to the film in a peeling direction.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: March 18, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara, Shoji Nishida, Kenji Yamagata
  • Patent number: 6517697
    Abstract: A holder (102) made from an HF-resistant material includes annular suction pads (105, 108). The suction pad (105) is used to hold a small silicon substrate by suction, and the suction pad (108) is used to hold a large silicon substrate by suction. This makes silicon substrates with various sizes processable. A silicon substrate is held by suction by reducing a pressure in a space in a groove of the suction pad by a pump (120). An opening (103) is formed in the holder (102) so that the both surfaces of the silicon substrate are brought into contact with an HF solution (115). The silicon substrate is anodized by applying a DC voltage by using a platinum electrode (109a) as a negative electrode and a platinum electrode (109b) as a positive electrode, and thereby a substrate having a porous layer is produced.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: February 11, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenji Yamagata
  • Publication number: 20020182038
    Abstract: The spaces in chuck grooves 3a and 3b are evacuated to chuck the entire surface of a wafer 1 to the chuck surface of a wafer support table 3 and curve the wafer 1. A wafer 2 is horizontally opposed to the wafer 1, and the center of the wafer 2 is pressed by a press pin 6a. The centers of the two wafers 1 and 2 are contacted, and the contact portion gradually spreads to the vicinity of the periphery of a central portion 3c and takes a substantially circular shape. After that, the chuck by the chuck grooves 3a is stopped. Consequently, the wafer 1 flattens, and the entire surfaces of the wafers 1 and 2 are contacted.
    Type: Application
    Filed: July 29, 2002
    Publication date: December 5, 2002
    Inventors: Toru Takisawa, Takao Yonehara, Kenji Yamagata
  • Patent number: 6451670
    Abstract: The spaces in chuck grooves 3a and 3b are evacuated to chuck the entire surface of a wafer 1 to the chuck surface of a wafer support table 3 and curve the wafer 1. A wafer 2 is horizontally opposed to the wafer 1, and the center of the wafer 2 is pressed by a press pin 6a. The centers of the two wafers 1 and 2 are contacted, and the contact portion gradually spreads to the vicinity of the periphery of a central portion 3c and takes a substantially circular shape. After that, the chuck by the chuck grooves 3a is stopped. Consequently, the wafer 1 flattens, and the entire surfaces of the wafers 1 and 2 are contacted.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: September 17, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toru Takisawa, Takao Yonehara, Kenji Yamagata
  • Patent number: 6428620
    Abstract: An object of this invention is to provide a substrate processing method capable of satisfactorily performing in etching in the step of removing a porous silicon layer by etching.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: August 6, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Yamagata, Kiyofumi Sakaguchi
  • Patent number: 6417069
    Abstract: A porous layer is formed on an Si substrate using an anodizing apparatus having a conductive partition inserted between a cathode and an anode. First, the cathode and Si substrate are brought into electrical contact through a first electrolyte, and the conductive partition and Si substrate are brought into electrical contact through a second electrolyte. A current is flowed between the cathode and the anode to form a porous layer on the Si substrate. As the first electrolyte, an electrolyte capable of forming a porous structure on the Si substrate is used. As the second electrolyte, an electrolyte substantially incapable of forming a porous structure on the conductive partition is used.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: July 9, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Satoshi Matsumura, Kenji Yamagata
  • Patent number: 6410436
    Abstract: In order to clean a porous body in a short time without causing any change in its structure, the porous body is cleaned after the anodization is completed with a cleaning solution containing at least one of an alcohol and acetic acid.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: June 25, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Yamagata, Satoshi Matsumura
  • Patent number: 6383890
    Abstract: Two wafers are properly brought into contact with each other. The first wafer is supported by a wafer support table (3) having an annular peripheral portion (3d). The substrate support table (3) is in contact with only the peripheral portion (3d) of the first wafer. While the second wafer opposing the first wafer is supported, the lower surface of the second wafer is pressed near its central portion, so the first and second wafers come into contact with each other outward from the central portion. The central portion (3c) of the wafer support table (3) is not in contact with the first wafer. Even when particles adhere to the central portion, unevenness on the supported first wafer can be prevented. Therefore, no gas is left between the wafers. This invention also provides a wafer support table formed by fabricating a silicon wafer. A commercially available silicon wafer is fabricated by lithography to prepare a wafer support table (31).
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: May 7, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toru Takisawa, Takao Yonehara, Kenji Yamagata
  • Publication number: 20020034859
    Abstract: The spaces in chuck grooves 3a and 3b are evacuated to chuck the entire surface of a wafer 1 to the chuck surface of a wafer support table 3 and curve the wafer 1. A wafer 2 is horizontally opposed to the wafer 1, and the center of the wafer 2 is pressed by a press pin 6a. The centers of the two wafers 1 and 2 are contacted, and the contact portion gradually spreads to the vicinity of the periphery of a central portion 3c and takes a substantially circular shape. After that, the chuck by the chuck grooves 3a is stopped. Consequently, the wafer 1 flattens, and the entire surfaces of the wafers 1 and 2 are contacted.
    Type: Application
    Filed: August 24, 1998
    Publication date: March 21, 2002
    Inventors: TORU TAKISAWA, TAKAO YONEHARA, KENJI YAMAGATA
  • Publication number: 20020016067
    Abstract: In order to clean a porous body in a short time without causing any change in its structure, in a cleaning method of cleaning a porous body formed by anodization, the porous body is cleaned after the anodization is completed, with a cleaning solution containing at least one of an alcohol and acetic acid.
    Type: Application
    Filed: March 16, 2000
    Publication date: February 7, 2002
    Inventors: Kenji Yamagata, Satoshi Matsumura