Patents by Inventor Kenji Yamagata

Kenji Yamagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020001920
    Abstract: Two wafers are properly brought into contact with each other. The first wafer is supported by a wafer support table (3) having an annular peripheral portion (3d). The substrate support table (3) is in contact with only the peripheral portion (3d) of the first wafer. While the second wafer opposing the first wafer is supported, the lower surface of the second wafer is pressed near its central portion, so the first and second wafers come into contact with each other outward from the central portion. The central portion (3c) of the wafer support table (3) is not in contact with the first wafer. Even when particles adhere to the central portion, unevenness on the supported first wafer can be prevented. Therefore, no gas is left between the wafers. This invention also provides a wafer support table formed by fabricating a silicon wafer. A commercially available silicon wafer is fabricated by lithography to prepare a wafer support table (31).
    Type: Application
    Filed: December 15, 1998
    Publication date: January 3, 2002
    Inventors: TORU TAKISAWA, TAKAO YONEHARA, KENJI YAMAGATA
  • Patent number: 6309505
    Abstract: One wafer is placed on a wafer support table with its frontside facing upward, and the other wafer is chucked by a wafer chuck portion with its frontside facing upward. The wafer chuck portion is pivoted about a shaft through about 180° to make the two wafers face each other substantially parallel. In response to the cancel of the chucking of the upper wafer by the wafer chuck portion, the central portion of the upper wafer is pressed by a press pin to superimpose the two wafers.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: October 30, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toru Takisawa, Takao Yonehara, Kenji Yamagata
  • Patent number: 6258240
    Abstract: It is an object of the present invention to provide an anodizing apparatus capable of efficiently performing anodizing. In order to achieve this object, an anodizing apparatus for anodizing a substrate to be processed in an electrolytic solution includes a process tank for storing the electrolytic solution, the process tank having an opening in a wall, a negative electrode arranged in the process tank to oppose the opening, and a positive electrode contacting a surface of the substrate to be processed which is arranged to close the opening from an inside of the process tank, the surface being open outside the process tank through the opening.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: July 10, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoshi Matsumura, Kenji Yamagata
  • Patent number: 6202655
    Abstract: A holder (102) made from an HF-resistant material includes annular suction pads (105, 108). The suction pad (105) is used to hold a small silicon substrate by suction, and the suction pad (108) is used to hold a large silicon substrate by suction. This makes silicon substrates with various sizes processable. A silicon substrate is held by suction by reducing a pressure in a space in a groove of the suction pad by a pump (120). An opening (103) is formed in the holder (102) so that the both surfaces of the silicon substrate are brought into contact with an HF solution (115). The silicon substrate is anodized by applying a DC voltage by using a platinum electrode (109a) as a negative electrode and a platinum electrode (109b) as a positive electrode, and thereby a substrate having a porous layer is produced.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: March 20, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenji Yamagata
  • Patent number: 6200878
    Abstract: An object of this invention is to provide a substrate processing method capable of satisfactorily performing in etching in the step of removing a porous silicon layer by etching.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: March 13, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Yamagata, Kiyofumi Sakaguchi
  • Patent number: 6156624
    Abstract: This invention solves the problem of a pasted SOI substrate generating voids in the peripheral part thereof and consequently decreasing the number of devices to be derived therefrom. It concerns a method for the production of a SOI substrate obtained by pasting a first Si substrate possessing a SiO.sub.2 surface and a second substrate possessing a Si surface on the SiO.sub.2 surface and the Si surface, which method comprises washing the Si surface of the second Si substrate, thereby imparting hydrophobicity to the Si surface before the first Si substrate and the second Si substrate are pasted together.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: December 5, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Yamagata, Takao Yonehara, Tadashi Atoji, Kiyofumi Sakaguchi
  • Patent number: 6103598
    Abstract: A process for producing a semiconductor substrate is provided which comprises providing a first substrate made of silicon having a porous silicon layer formed thereon by making porous the substrate silicon and a nonporous monocrystalline silicon layer epitaxially grown on the porous silicon layer, laminating the first substrate onto a second substrate in a state that at least one of lamination faces of the first and the second substrates has a silicon oxide layer and the nonporous monocrystalline silicon layer is interposed between the laminated substrates, and removing the porous silicon layer by etching, wherein the porous silicon layer is removed by etching with an etchant which etches the nonporous monocrystalline silicon layer and the silicon oxide layer at respective etching rates of not more than 10 angstroms per minute.
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: August 15, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Yamagata, Takao Yonehara, Nobuhiko Sato, Kiyofumi Sakaguchi
  • Patent number: 6100166
    Abstract: A process for producing a semiconductor article is provided which comprises the steps of bonding a film onto a substrate having a porous semiconductor layer, and separating the film from the substrate at the porous semiconductor layer by applying a force to the film in a peeling direction.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: August 8, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara, Shoji Nishida, Kenji Yamagata
  • Patent number: 5980633
    Abstract: A bonded substrate and a process for its production is provided to solve the problem involved in the heat treatment which tends to cause troubles such as break, separation and warpage of the substrates bonded. A single-crystal semiconductor epitaxially grown on a porous semiconductor substrate is bonded to an insulator substrate, and the semiconductor substrate is removed by etching, grinding, or a combination of the both, where no heat treatment is carried out or, even if carried out, only once.
    Type: Grant
    Filed: July 23, 1997
    Date of Patent: November 9, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Yamagata, Takao Yonehara
  • Patent number: 5951833
    Abstract: A holder (102) made from an HF-resistant material includes annular suction pads (105, 108). The suction pad (105) is used to hold a small silicon substrate by suction, and the suction pad (108) is used to hold a large silicon substrate by suction. This makes silicon substrates with various sizes processable. A silicon substrate is held by suction by reducing a pressure in a space in a groove of the suction pad by a pump (120). An opening (103) is formed in the holder (102) so that the both surfaces of the silicon substrate are brought into contact with an HF solution (115). The silicon substrate is anodized by applying a DC voltage by using a platinum electrode (109a) as a negative electrode and a platinum electrode (109b) as a positive electrode, and thereby a substrate having a porous layer is produced.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: September 14, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenji Yamagata
  • Patent number: 5695557
    Abstract: A bonded substrate and a process for its production is provided to solve the problem involved in the heat treatment which tends to cause troubles such as break, separation and warpage of the substrates bonded. A single-crystal semiconductor epitaxially grown on a porous semiconductor substrate is bonded to an insulator substrate, and the semiconductor substrate is removed by etching, grinding, or a combination of the both, where no heat treatment is carried out or, even if carried out, only once.
    Type: Grant
    Filed: December 28, 1994
    Date of Patent: December 9, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Yamagata, Takao Yonehara
  • Patent number: 5679475
    Abstract: A process for preparing a semiconductor substrate comprises a step of porousifying a silicon monocrystalline substrate to form a porous layer, a step of making a silicon monocrystalline thin film to epitaxially grow on a surface of the porous layer, a step of oxidizing the surface of the epitaxial growth layer, a step of forming a deposited film on the oxidized surface, thereby obtaining a first substrate, a step of closely contacting the deposited film of the first substrate to a second substrate, a step of heat treating the closely contacted substrates and a step of selectively etching the porous layer.
    Type: Grant
    Filed: January 4, 1995
    Date of Patent: October 21, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Yamagata, Takao Yonehara
  • Patent number: 5670411
    Abstract: A process for forming a semiconductor substrate wherein an epitaxial layer is formed on a porous layer of a first substrate, an insulating layer is formed on the epitaxial layer, the insulating layer is bonded to a second substrate and the porous layer is selectively removed.
    Type: Grant
    Filed: May 18, 1995
    Date of Patent: September 23, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Kenji Yamagata
  • Patent number: 5653802
    Abstract: A method for forming a crystal comprises implanting ions on the surface of a substrate to change the ion concentration in the depth direction of said substrate surface by said ion implantation, subjecting a desired position of said substrate surface with a sufficient area for crystal growth from a single crystal to exposure treatment to/he depth where an exposed surface having larger nucleation density than the nucleation density of the surface of said substrate is exposed, thereby forming a nucleation surface comprising said exposed surface exposed by said exposure treatment and a nonnucleation surface comprising the surface of the substrate remaining without subjected to said exposure treatment, applying a crystal growth treatment for crystal growth from a single nucleus on said substrate to grow a single crystal from said single nucleus or form a polycrystal of a mass of single crystals grown from said single nucleus.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: August 5, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenji Yamagata
  • Patent number: 5580381
    Abstract: A crystal forming method comprises disposing, on a surface of a substrate or in recessed portion formed in the substrate having a surface with a low nucleation density, primary seed having a sufficient small volume to singly aggregate and a rectangular prismatic or cubic shape in which all the sides and the bottom are surrounded by an insulator in contact therewith; performing heat treatment for aggregating the primary seed to form monocrystalline seed crystal having controlled plane orientation and in-plane orientation; and selectively growing monocrystal by crystal growth treatment using the seed crystal as starting point.
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: December 3, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenji Yamagata
  • Patent number: 5466631
    Abstract: A method for producing a semiconductor article comprises the steps of preparing a first substrate having a non-porous semiconductor layer on a porous semiconductor region, forming unevenness on the surface at the side of said semiconductor layer of said first substrate; bonding the surface of said first substrate having said unevenness formed thereon to the surface of said second substrate so as to be in contact with each other, and removing said porous semiconductor under the state that said semiconductor layer is bonded to said second substrate to thereby transfer said semiconductor layer from said first substrate onto said second substrate.
    Type: Grant
    Filed: February 23, 1995
    Date of Patent: November 14, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Ichikawa, Takao Yonehara, Masaru Sakamoto, Yasuhiro Naruse, Jun Nakayama, Kenji Yamagata, Kiyofumi Sakaguchi
  • Patent number: 5453394
    Abstract: A process for preparing a semiconductor substrate comprises bringing a first substrate provided with at least one of boron and phosphorus on the surface of an insulating layer formed on the surface of the substrate in contact with a second substrate, and integrating both of the substrates by a heat treatment.
    Type: Grant
    Filed: January 28, 1993
    Date of Patent: September 26, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Kenji Yamagata
  • Patent number: 5447117
    Abstract: A crystal article comprises a substrate having an insulating amorphous surface and monocrystal formed on the substrate. The monocrystal is formed by providing a primary seed in the form of a film with an area 100 .mu.m.sup.2 or less arranged in a desired pattern on the surface of the substrate acting as a non-nucleation surface with a small nucleation density, then subjecting the primary seed to thermal treatment to convert it to a monocrystalline seed, and subsequently subjecting the monocrystalline seed to crystal growth treatment to allow a monocrystal to grow beyond the monocrystalline seed and cover the non-nucleation surface.
    Type: Grant
    Filed: October 24, 1994
    Date of Patent: September 5, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Kenji Yamagata, Yuji Nishigaki
  • Patent number: 5405802
    Abstract: A process for preparing a semiconductor substrate comprises a step of porousifying a silicon monocrystalline substrate to form a porous layer, a step of making a silicon monocrystalline thin film to epitaxially grow on a surface of the porous layer, a step of oxidizing the surface of the epitaxial growth layer, a step of forming a deposited film on the oxidized surface, thereby obtainig a first substrate, a step of closely contacting the deposited film of the first substrate to a second substrate, a step of heat treating the closely contacted substrates and a step of selectively etching the porous layer.
    Type: Grant
    Filed: May 25, 1994
    Date of Patent: April 11, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Yamagata, Takao Yonehara
  • Patent number: 5403751
    Abstract: A process for the production of a solar cell, characterized in that the surface of a silicon wafer is periodically exposed through minute spaced portions of an insulating layer formed on the silicon wafer; crystal growth is performed until monocrystalline silicon regions caused at the spaced portions by way of selective epitaxial growth and lateral crystal growth become collided with each other; the insulating layer is removed through gaps left among the monocrystals; a resin is embedded in the gaps; an electrode layer is formed over the surfaces of the monocrystalline silicon regions; the surface of the electrode layer is fastened to a substrate through a resin; a body comprising the monocrystalline silicon regions is separated from the silicon wafer; and a counter electrode is disposed to the monocrystalline silicon regions.
    Type: Grant
    Filed: June 20, 1994
    Date of Patent: April 4, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shoji Nishida, Kenji Yamagata