Patents by Inventor Kenji Yoneda

Kenji Yoneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6407281
    Abstract: A process for producing optically active cysteine derivatives with high optical purity and good quality which is economically advantageous and is high in productivity even on a commercial scale is provided.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: June 18, 2002
    Assignee: Kaneka Corporation
    Inventors: Yasuyoshi Ueda, Hiroshi Murao, Takeshi Kondo, Noboru Ueyama, Hajime Manabe, Kenji Yoneda, Akira Nishiyama
  • Publication number: 20020019101
    Abstract: A silicon germanium layer is deposited over a semi-conductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. Then, an upper silicon layer in an amorphous state is deposited on the silicon germanium layer. Thereafter, a gate electrode is formed by patterning the silicon germanium layer and the upper silicon layer.
    Type: Application
    Filed: July 25, 2001
    Publication date: February 14, 2002
    Inventors: Hiroko Kubo, Kenji Yoneda
  • Publication number: 20010028452
    Abstract: The unit for inspecting a surface is to detect a flaw on a specular surface of an object to be inspected with accuracy. The unit is so arranged that light 1a is irradiated from a point light source or close to a point light source 4, the light 1a is refracted by a Fresnel lens 5 so as to converge in a condition of being close to parallel, the refracted light 1a is reflected by a half mirror 6, the light 1a is irradiated on generally whole area of the specular surface 2 to be inspected and the reflected light 1a is introduced into an image capturing means 10 provided at a position where the light 1a converges.
    Type: Application
    Filed: December 22, 2000
    Publication date: October 11, 2001
    Inventor: Kenji Yoneda
  • Patent number: 6265327
    Abstract: Disclosed are a method and apparatus for forming an insulating film on the surface of a semiconductor substrate capable of improving the quality and electrical properties of the insulating film with no employment of high-temperature heating and with good controllability. After the surface of a silicon substrate is cleaned, a silicon dioxide film having a thickness of 1-20 nm is formed on the substrate surface. The silicon substrate is exposed to plasma generated by electron impact, while the silicon substrate is maintained at a temperature of 0° C. to 700° C. Thus, nitrogen atoms are incorporated into the silicon dioxide film, obtaining a modified insulating film having good electrical properties.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: July 24, 2001
    Assignees: Japan Science and Technology Corp., Matsushita Electronics Corp.
    Inventors: Hikaru Kobayashi, Kenji Yoneda
  • Patent number: 6266660
    Abstract: A secondary index search in a relational database system compares primary key selection criteria against a primary key value stored in a secondary index record that satisfies secondary key selection criteria instead of searching a primary index for a primary key value that satisfies the primary key selection criteria.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: July 24, 2001
    Assignee: Unisys Corporation
    Inventors: Lee-Chin Hsu Liu, Kenji Yoneda
  • Patent number: 6263331
    Abstract: A hybrid hash join process joins data rows from two tables which have at least one common data column by partitioning the data rows based on the values in the common data column(s), creating data structures to decrease search time for matching rows, and recovering full data buffers using a unique buffer management methodology. A smaller one of the two tables is designated as an outer table and a larger one of the two tables as an inner table. The hybrid hash join process determines which rows in the inner and outer tables satisfy a selection criteria; the rows that satisfy the selection criteria are referred to as inner hit rows and outer hit rows. The hybrid hash join process assigns the inner and outer hit rows to corresponding inner and outer partitions, respectively. Buffer overflow in the outer partitions is handled by linking empty buffers to the outer partitions until all buffers are used. Buffer space is recovered by writing outer hit rows for a selected partition to mass storage.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: July 17, 2001
    Assignee: Unisys Corporation
    Inventors: Lee-Chin Hsu Liu, Lowell L. Baerenwald, James M. Plasek, Michael S. Jende, Kenji Yoneda
  • Patent number: 6221788
    Abstract: The semiconductor of the present invention comprises at least an oxide film and a metal thin film on the surface of the semiconductor. The metal thin film includes a metal serving as an oxidation catalyst and has a thickness in the range of 0.5-30 nm. The oxide film comprises a metal serving as an oxidation catalyst and having a thickness in the range of 1-20 nm. Thus, a high-quality oxide film can be formed on the surface of the semiconductor substrate with high controllability without conducting a high temperature heat treatment. The invention employs the method of manufacturing the semiconductor has a steps of forming the first oxidation film having thickness in the range of 0.1-2.5 nm on the semiconductor substrate; forming the metal thin film (for example platinum film) serving as an oxide catalyst to the thickness in the range of 0.5-30 nm on the first oxide thin film; and then forming the second oxide film by heat treating in an oxidizing atmosphere at temperatures from 25 to 600° C.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: April 24, 2001
    Assignees: Matsushita Electronics Corporation, Hikaru Kobayashi
    Inventors: Hikaru Kobayashi, Kenji Yoneda, Takashi Namura
  • Patent number: 6168296
    Abstract: An object of the invention is to obtain a lighting unit for reading marks which makes it possible with accuracy to read a mark carved on a surface of a base whose surface is specular finished. A lighting unit for reading marks in accordance with the invention comprises two light sources 51 and 52 and a light parallel means 6 which makes rays of light emitted from each of the light sources 51 and 52 parallel or generally parallel respectively. Each of the rays of light emitted from the light sources 51 and 52 are made parallel respectively by the light parallel means 6 and irradiated on two areas 18 and 19 of the base 3 and the two areas 18 and 9 face each other across the mark 4 carved on the base 3.
    Type: Grant
    Filed: June 22, 1998
    Date of Patent: January 2, 2001
    Assignee: CCS Co., Ltd.
    Inventor: Kenji Yoneda
  • Patent number: 6087379
    Abstract: A cyclic amine derivative represented by the following formula: ##STR1## wherein R.sup.1 represents a substituted or unsubstituted phenyl group, R.sup.2 represents a substituted of unsubstituted C.sub.1 -C.sub.8 aliphatic acyl group, a substituted or unsubstituted benzoyl group or a C.sub.1 -C.sub.4 alkoxycarbonyl group, and R.sup.3 represents a substituted 3 to 7 membered saturated cyclic amino group which may form a fused ring; or pharmaceutically acceptable salts thereof. The compounds and salts have excellent platelet aggregation inhibitory action. They are useful for the treatment and prevention of such diseases as embolism, thrombosis or arteriosclerosis and for the preparation of pharmaceutical compositions for such uses.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: July 11, 2000
    Assignees: Sankyo Company, Limited, Ube Industries, Ltd.
    Inventors: Fumitoshi Asai, Atsuhiro Sugidachi, Toshihiko Ikeda, Hiroyuki Koike, Teruhiko Inoue, Katsunori Takata, Ryo Iwamura, Jun-ichiro Kita, Kenji Yoneda
  • Patent number: 6070986
    Abstract: An object of the invention is to make it easy to manufacture the lighting unit 4 in which a plurality of illuminants 1 are arranged on the concave face of a board 2 formed into a shape of a hollow truncated cone. A method of manufacturing a lighting unit comprises the steps of holding a flexible circular printed circuit board 2 having a concentric circular hole and a cutout which has at least two sides 2a, 2b in a planar state, embedding a plurality of illuminants 1 in the board, and jointing one side 2a of the cutout and the other side 2b of the cutout or holding both sides 2a, 2b in close contact so as to place the illuminants 1 in the side of the concave face of the board 2.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: June 6, 2000
    Assignee: CCS Co., Ltd.
    Inventor: Kenji Yoneda
  • Patent number: 6053621
    Abstract: A lighting unit for examining the quality of a product, wherein the lighting unit can be easily assembled, has a small number of components, and emits light from a surface at a light intensity with little unevenness. An illuminant assembly of the lighting unit comprises a ring-shaped transparent body for light diffusion, and a plurality of illuminants such as light-emitting diodes that are positioned along the periphery of the transparent body and are capable of emitting light toward the center of the transparent body. Light emitted from the illuminants passes through the transparent body while being reflected and scattered, and is emitted uniformly from an underside surface of the transparent body, providing emission of light from a surface at an even light intensity.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: April 25, 2000
    Assignee: CCS Co., Ltd.
    Inventor: Kenji Yoneda
  • Patent number: 6022813
    Abstract: There are disclosed a method and apparatus for manufacturing semiconductor devices. The surface of each semiconductor substrate is exposed to cyanide ions (CN.sup.-) in order to reduce the density of interface states at the insulating film/semiconductor interface. For this purpose, the semiconductor substrate is immersed into a cyan compound solution or is exposed to a cyan compound gas, so that cyanide ions (CN.sup.-) are bonded to dangling bonds at the surface of the semiconductor substrates. As a result, the interface states at the insulating film/semiconductor interface can be reduced.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: February 8, 2000
    Assignees: Japan Science and Technology Corporation, Matsushita Electronics Corporation
    Inventors: Hikaru Kobayashi, Kenji Yoneda
  • Patent number: 5896875
    Abstract: An equipment for cleaning, etching and drying a semiconductor wafer is provided with a process chamber having a closed space of which temperature is capable of being heated and adjusted by a heater; a mesh arranged at the center part in the process chamber and supporting at least one semiconductor wafer to be cleaned; a plurality of spray nozzles arranged in line at the upper part in the process chamber; and a rotary discharge nozzle arranged at the lower part in the process chamber. The spray nozzles spray chemical and ultrapure water with nitrogen gas in mist state, and the rotary discharge nozzle blows out chemical and ultrapure water as jet stream by rotation of a first arm and second arms thereof.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: April 27, 1999
    Assignee: Matsushita Electronics Corporation
    Inventor: Kenji Yoneda
  • Patent number: 5892190
    Abstract: Elevator group supervisory control method and system for group supervisory control of a plurality of elevators serving a plurality of floors. The method and apparatus of the invention permits the inputting of qualitative requests (guidance), from the user, concerning elevator operation into the group supervisory control system. Qualitative requests concerning elevator operation are set in the form of guidance (or request) targets. The thus set request targets are converted into control targets for the elevators. Actual group supervisory control is executed using the control targets.
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: April 6, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Yuzo Morita, Toshimitsu Tobita, Kiyoshi Nakamura, Atsuya Fujino, Soshiro Kuzunuki, Kotaro Hirasawa, Yoshio Sakai, Kenji Yoneda, Takaaki Ueshima, Yuji Toda, Hiromi Inaba
  • Patent number: 5648282
    Abstract: To form a MOS transistor with a LDD structure, the transistor is formed in a well region. There is formed a gate oxide layer on a silicon substrate and an N.sup.+ type poly-silicon layer serving as a gate electrode is formed on the gate oxide layer. The poly-silicon layer is doped with phosphorus atoms. Then, a surface of the silicon substrate is exposed in a LDD region serving as a source/drain region as formed with phosphorus implantation. The LDD region of the transistor is implanted with phosphorus ions. Subsequently, a side wall is formed on the gate electrode. To enhance the adherence of the side wall material and activate the phosphorus ions implanted in the previous step, annealing and formation of an oxide film are effected. This thermal treatment prevents the phosphorus atoms from deporting the gate electrode of the poly-silicon layer and self diffusing into the LDD region. This thermal treatment is performed with nitrogen gas containing 1 to 5 volume % at the initial stage thereof.
    Type: Grant
    Filed: May 24, 1993
    Date of Patent: July 15, 1997
    Assignee: Matsushita Electronics Corporation
    Inventor: Kenji Yoneda
  • Patent number: 5409085
    Abstract: The present invention relates to a group control elevator system which has been adjusted to operate in response to a state of utilizing elevator cars. In a group control elevator system which carries out a control of allocating elevator cars to elevator car calls for serving many floors by using an evaluation function having a plurality of variable parameters, targets for elevator control performance are inputted, a traffic flow to which elevator car demand belongs is judged, variable parameters to be adjusted which have been set in advance for each combination of said targets and traffic flows are stored, stored variable parameters are adjusted, adjustment sequence of variable parameters to be adjusted is stored, and a plurality of variable parameters are sequentially adjusted according to the stored sequence. By the above arrangement, only desired parameters to be adjusted are selected and adjusted out of a plurality of variable parameters for desired targets and traffic flows.
    Type: Grant
    Filed: November 24, 1993
    Date of Patent: April 25, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Atsuya Fujino, Toshimitsu Tobita, Hiromi Inaba, Kiyoshi Nakamura, Yoshio Sakai, Kenji Yoneda, Hiroaki Yamani
  • Patent number: 5370216
    Abstract: An apparatus for aligning vessels comprises a robot for delivering a vessel from a first conveyor to a second conveyor, a camera disposed on a path of conveyance of the first conveyor for photographing a manner of placement of vessels thereon, and correction device mounted on the second conveyor for erecting a vessel assuming a horizontal position when it is released by the robot. Any change in the size of a vessel does not require a remodelling of components of the apparatus, thus providing a vessel aligning apparatus having a high versatility.
    Type: Grant
    Filed: February 22, 1994
    Date of Patent: December 6, 1994
    Assignee: Shibuya Kogyo Co., Ltd.
    Inventors: Katsuji Tsuruyama, Masaki Murahama, Kenji Yoneda
  • Patent number: 5307903
    Abstract: Elevator group supervisory control method and system for group supervisory control of a plurality of elevators serving a plurality of floors. The method and apparatus of the invention permits the inputting of qualitative requests (guidance), from the user, concerning elevator operation into the group supervisory control system. Qualitative requests concerning elevator operation are set in the form of guidance (or request) targets. The thus set request, targets are converted into control targets for the elevators. Actual group supervisory control is executed using the control targets.
    Type: Grant
    Filed: January 26, 1989
    Date of Patent: May 3, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Yuzo Morita, Toshimitsu Tobita, Kiyoshi Nakamura, Atsuya Fujino, Soshiro Kuzunuki, Kotaro Hirasawa, Yoshio Sakai, Kenji Yoneda, Takaaki Ueshima, Yuji Toda, Hiromi Inaba
  • Patent number: D447159
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: August 28, 2001
    Assignee: CCS Inc.
    Inventor: Kenji Yoneda
  • Patent number: D460095
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: July 9, 2002
    Assignee: CCS Co., Ltd.
    Inventor: Kenji Yoneda