Abstract: A capping layer is on top of a substrate. A first low-k dielectric layer is on top of the capping layer. One or more trenches are within the first low-k dielectric layer. Each of the one or more trenches have a same depth. Each trench of the one or more trenches include a barrier layer on top of the first low-k dielectric layer, a liner layer and a metal layer on top of the liner layer.

Abstract: A semiconductor structure may include a metal line, a via above and in electrical contact with the metal lines, and a dielectric layer positioned along a top surface of the metal lines. A top surface of the dielectric layer may be below the dome shaped tip of the via. A top portion of the via may include a dome shaped tip. The semiconductor structure may include a liner positioned along the top surface of the dielectric layer and a top surface of the dome shaped tip of the via. The liner may be made of tantalum nitride or titanium nitride. The dielectric layer may be made of a low-k material. The metal line and the via may be made of ruthenium. The metal line may be made of molybdenum.

Abstract: A method of forming a memory device with a laterally-recessed free layer includes forming a bottom electrode above an electrically conductive structure embedded within an interconnect dielectric material. A magnetic tunnel junction stack is formed above the bottom electrode. Forming the magnetic tunnel junction stack includes forming a magnetic reference layer above the bottom electrode, forming a tunnel barrier layer above the magnetic reference layer, and forming a magnetic free layer above the tunnel barrier layer. Opposed lateral portions of the magnetic free layer are recessed, and sidewall spacers are formed on the recessed opposed lateral portions of the magnetic free layer for confining an active region of the memory device formed by the magnetic free layer and the tunnel barrier layer.

Abstract: A memory device, and a method of forming the same, includes a bottom electrode above an electrically conductive structure, the electrically conductive structure is embedded in an interconnect dielectric material. A magnetic tunnel junction stack located above the bottom electrode is formed by a magnetic reference layer above the bottom electrode, a tunnel barrier layer above the magnetic reference layer, and a laterally-recessed magnetic free layer above the tunnel barrier layer. Sidewall spacers surround the laterally-recessed magnetic free layer for confining an active region formed by the laterally-recessed magnetic free and the tunnel barrier layer.

Abstract: An antifuse structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line, and a conductive etch stop layer separating both the first metal line and the second metal line from an underlying layer, where a first portion of the conductive etch stop layer directly beneath the first metal line comprises a first extension region and a second portion of the conductive etch stop layer directly beneath the second metal line comprises a second extension region opposite the first extension region.

Abstract: A method for manufacturing a semiconductor device includes forming an interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. A trench and an opening are formed in the third and second dielectric layers, respectively. A barrier layer is deposited in the trench and in the opening, and on a top surface of the interconnect. The method also includes removing the barrier layer from the top surface of the interconnect and from a bottom surface of the trench, and depositing a conductive fill layer in the trench and in the opening, and on the interconnect. A bottom surface of the trench includes the etch stop layer.

Abstract: A semiconductor structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line adjacent to the first metal line, a first dielectric contacting sidewalls of the top via, a second dielectric directly between the first dielectric and the second metal line, and an air gap located between the first metal line and the second metal line, and below both the first dielectric and the second dielectric.

Abstract: A structure and a method for fabricating interconnections for an integrated circuit device are described. The method forms a metal interconnection pattern having a first barrier layer and a copper layer in a set of trenches in a first dielectric layer over a substrate. In a selected area, the first dielectric layer is removed to so that the first barrier layer can be removed at the exposed vertical surfaces. A thin second barrier layer is deposited over the exposed vertical surfaces of the first copper layer. A structure includes a first feature formed in a first dielectric layer which has a first barrier layer disposed on vertical surfaces of the first dielectric layer and surrounds opposing vertical surfaces and a bottom surface of a copper layer.

Abstract: A first metal interconnection pattern is formed over a substrate. A spacer layer is selectively deposited on the exposed surfaces of the first metal interconnection pattern. Subsequently, a metal overburden layer is deposited on the spacer layer. The excess portion of the metal overburden layer is removed, i.e., that portion deposited over a top surface of the metal interconnection pattern and the spacer layer. This forms a second metal interconnection pattern. The elements of the second metal interconnection pattern are located between respective elements of the first metal interconnection pattern.

Abstract: An electrical communication structure that includes a plurality of metal line levels, a first metal line in a first metal line level of the plurality of line levels, and a second metal line in an upper metal line level of the plurality of line levels. A base of the second metal line is atop a metal etch stop layer that is aligned with edges of the second metal line. The electrical communication structure further includes a via that extends from the first metal line to the second metal line through the plurality of line levels. the via is not in electrical communication with at least one an intermediate metal line within the plurality of line levels between the first metal line level and the upper metal line level. The via has a metal fill that is in direct contact with a metal fill of the first metal line.

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes a metal line layer and a top via layer that each include a plurality of alternating first layers composed of a first metal and second layers composed of a second metal, whereby the second layers are thinner than the first layers.

Abstract: A MIM capacitor and related methods of fabricating the MIM capacitor. The MIM capacitor includes a bottom capacitor plate including a plurality of trenches defined therein, and a top capacitor plate. The MIM capacitor also includes a capacitor insulating layer disposed between the top capacitor plate and the bottom capacitor plate and within the plurality of trenches. Further, the MIM capacitor includes a first electrode electrically connected to the bottom capacitor plate, and a second electrode electrically connected to the top capacitor plate.

Abstract: The structure comprises a first low-k dielectric layer on top of a substrate. The structure comprises one or more trenches within the first low-k dielectric layer. The structure comprises a first barrier layer on the first low-k dielectric layer, a first liner layer on top of the first barrier layer and a first metal layer on top of the first liner layer, wherein a top of the first barrier layer, the first liner layer, and the first metal layer are at least 5 nm below a top of the first low-k dielectric layer. The structure comprises a dielectric cap between portions the first low-k dielectric layer and a second low-k dielectric layer. The structure comprises a dielectric plug between portions of the first low-k dielectric layer and the second low-dielectric layer.

Abstract: Disclosed is a memory device. The memory device comprises a cross-bar array of memory cells. The cross-bar array of memory cells comprises a plurality of bottom level lines arranged in a first direction. The cross-bar array of memory cells further comprises a plurality of vias arranged on top of each of the plurality of bottom level lines. The cross-bar array of memory cells further comprises a plurality of memory cells. Each memory cell is arranged on top of one of the plurality of vias. The cross-bar array of memory cells further comprises a plurality of top level lines arranged in a second direction that is substantially perpendicular to the first direction. Each top level line is arranged on top of and electrically connected to two or more memory cells.

Abstract: A memory device includes a bottom electrode having an uppermost surface, a first sidewall, and a second sidewall. The memory device further includes a dielectric layer covering the uppermost surface and the first and second sidewalls of the bottom electrode such that an uppermost surface of the dielectric layer is arranged higher than the uppermost surface of the bottom electrode. The memory device further includes a metal body in direct contact with the uppermost surface of the bottom electrode and extending through the dielectric layer to the uppermost surface of the dielectric layer. The memory device further includes a memory component arranged in direct contact with the metal body and with the uppermost surface of the dielectric layer.

Abstract: An interconnect structure is provided the includes a top electrically conductive via structure that is fully-aligned to a bottom electrically conductive line structure. The interconnect structure has a maximized contact area between the top electrically conductive via structure and the bottom electrically conductive line structure without metal fangs that are caused by over etching. The dielectric surface of the interconnect dielectric material layer that is adjacent to the top electrically conductive via structure is free of reactive ion etch (RIE) damage. Further, there is no line wiggling since the bottom electrically conductive line structure is formed by a substrative metal etch. Further, there is no via distortion since the via opening used to house the top electrically conductive via structure has a density and aspect ratio that are low enough to avoid via distortion.

Abstract: A fully-aligned via interconnect structure is provided in which a first etch stop layer is formed on a first interconnect dielectric material layer containing an electrically conductive line structure to protect the interconnect dielectric material from eroding during metallization used in providing a combined vialline electrically conductive structure in a second interconnect dielectric material layer that is formed above the first interconnect dielectric material layer. The interconnect structure has low resistance due to the maximized contact between the via portion of combined vialline electrically conductive structure and the underlying electrically conductive line structure. Moreover, no bowing or metal fangs are formed, and no metal residue is introduced into the first interconnect dielectric material layer during metallization.

Abstract: A method of making a semiconductor component includes forming an interconnect in a dielectric layer such that an uppermost surface of the interconnect is substantially coplanar with an uppermost surface of the dielectric layer. The method further includes recessing the dielectric layer such that the uppermost surface of the dielectric layer is lower than the uppermost surface of the interconnect. The method further includes forming spacers in direct contact with the uppermost surface of the recessed dielectric layer such that the spacers are in direct contact with the interconnect. The method further includes recessing the interconnect such that the uppermost surface of the interconnect remains above the uppermost surface of the recessed dielectric layer and is lower than an uppermost surface of the spacers.

Abstract: A copper interconnect with an embedded dielectric cap between lines comprises a plurality of interconnect lines formed in a dielectric layer of a semiconductor device. The copper interconnect further comprises a first dielectric cap formed between each interconnect line of the plurality of interconnect lines. The copper interconnect further comprises a second dielectric cap formed on top of the plurality of interconnect lines and the first dielectric cap, wherein the second dielectric cap formed on top of the first dielectric cap forms a bi-layer dielectric cap between the plurality of interconnect lines.

Abstract: A method of making a semiconductor component includes forming a lower level including an interconnect structure. The method includes forming an upper level including a first dielectric layer, a second dielectric layer, and a barrier layer arranged between the first and second dielectric layers. The method includes forming a cavity in the upper level such that a portion of the interconnect structure and a portion of the barrier layer are exposed. The method includes forming a barrier material on all surfaces exposed by the formation of the cavity. The method includes removing the barrier material from all substantially horizontal surfaces exposed by the formation of the cavity. The method includes filling the cavity with an interconnect material such that the interconnect material is in direct contact with the interconnect structure and the barrier layer.