Abstract: Interconnect structures and methods for forming the interconnect structures generally include forming a dielectric layer over a substrate. The dielectric layer includes a dielectric layer top surface. A metal line is formed in the dielectric layer. The metal line includes a sacrificial upper region and a lower region. The sacrificial upper region is formed separately from the lower region and the lower region includes a lower region top surface positioned below the dielectric layer top surface. The sacrificial upper region is removed, thereby exposing the lower region top surface and forming a trench defined by the lower region top surface and sidewalls of the dielectric layer. An interconnect structure is deposited such that at least a portion of the interconnect structure fills the trench, thereby defining a fully aligned top via.

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. The method also includes forming a trench in the third dielectric layer, wherein a bottom surface of the trench includes the etch stop layer. A second interconnect is formed in the trench on the etch stop layer, and a via is formed in the second dielectric layer. The via connects the second interconnect to the first interconnect.

Abstract: Techniques are provided to fabricate semiconductor devices. For example, a method includes forming a lower level interconnect line having a first hardmask layer thereon and embedded in a lower level dielectric layer. The first hardmask layer is removed to form a first opening having a first width in the lower level dielectric layer. The sidewalls of the lower level dielectric layer are etched in the first openings to form a second opening having a second width. The second width is greater than the first width. An upper level interconnect line is formed on the lower level interconnect line.

Abstract: A method for manufacturing a semiconductor device includes forming an interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. A trench and an opening are formed in the third and second dielectric layers, respectively. A barrier layer is deposited in the trench and in the opening, and on a top surface of the interconnect. The method also includes removing the barrier layer from the top surface of the interconnect and from a bottom surface of the trench, and depositing a conductive fill layer in the trench and in the opening, and on the interconnect. A bottom surface of the trench includes the etch stop layer.

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. The method also includes forming a trench in the third dielectric layer, wherein a bottom surface of the trench includes the etch stop layer. A second interconnect is formed in the trench on the etch stop layer, and a via is formed in the second dielectric layer. The via connects the second interconnect to the first interconnect.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of interconnects spaced apart from each other on a substrate. The plurality of interconnects each have an upper portion and a lower portion. In the method, a plurality of spacers are formed on sides of the upper portions of the plurality of interconnects. A space is formed between adjacent spacers of the plurality of spacers on adjacent interconnects of the plurality of interconnects. The method also includes forming a dielectric layer on the plurality of spacers and on the plurality of interconnects. The dielectric layer fills in the space between the adjacent spacers of the plurality of spacers, which blocks formation of the dielectric layer in an area below the space. The area below the space is between lower portions of the adjacent interconnects.

Abstract: An interconnect structure includes a first electrically conductive via portion on an upper surface of a substrate, the first electrically conductive via elongated along a first direction, and a first ILD material on the substrate and covering the first electrically conductive via portion. The first ILD material includes an ILD upper surface exposing a via surface of the first electrically conductive via portion. A second electrically conductive via portion is on the ILD upper surface and the via upper surface thereby defining a contact area between the first electrically conductive via portion and the second electrically conductive via portion. The second electrically conductive via portion elongated along a second direction orthogonal with respect to the first direction. A second ILD material is on the ILD upper surface to cover the second electrically conductive via portion. The first and second electrically conductive via portions are fully aligned at the contact area.

Abstract: A back end of line interconnect structure and methods for forming the interconnect structure including a fully aligned via design generally includes wide lines formed of copper and narrow lines formed of an alternative metal. The fully aligned vias are fabricated using a metal recess approach and the hybrid metal conductors can be fabricated using a selective deposition approach.

Abstract: A method includes forming a first metallization layer on a substrate comprising a plurality of conductive lines. The method further includes forming a first dielectric layer on the substrate and between adjacent conductive lines. The method further includes forming a first via layer comprising at least one via in the first dielectric layer and exposing a top surface of at least one of the plurality of conductive lines. The method further includes depositing a first conductive material in the first via. The method further includes forming a barrier layer on a top surface of the first dielectric layer and exposing a top surface of the plurality of conductive lines and the first conductive material.

Abstract: A method for manufacturing a semiconductor device includes forming first and second interconnect structures on an etch stop layer, wherein the second interconnect structure is spaced apart from the first interconnect structure. The etch stop layer extends between the first and second interconnect structures. In the method, part of the etch stop layer between the first and second interconnect structures is removed. The removing forms a first portion of the etch stop layer extending from under the first interconnect structure toward the second interconnect structure, and a second portion of the etch stop layer extending from under the second interconnect structure toward the first interconnect structure. The first and second portions are spaced apart from each other. A dielectric layer is formed which fills in the spaces between the first and second portions of the etch stop layer and between the first and second interconnect structures.

Abstract: A semiconductor structure includes a substrate. A first metallization layer is disposed on the substrate. A second metallization layer is disposed on the first metallization layer and having one or more openings, wherein at least one of the one or more openings is configured to expose a top surface of the first metallization layer. A polymer-adhering liner layer is disposed on sidewalls of the at least one of the one more openings in the second metallization layer. A dielectric polymer is disposed in the at least one of the one or more openings in the second metallization layer and on the polymer-adhering liner layer. The dielectric polymer is configured to seal an air gap in the dielectric polymer.

Abstract: Techniques are provided to fabricate semiconductor devices. For example, a method includes forming a lower level interconnect line having a first hardmask layer thereon and embedded in a lower level dielectric layer. The first hardmask layer is removed to form a first opening having a first width in the lower level dielectric layer. The sidewalls of the lower level dielectric layer are etched in the first openings to form a second opening having a second width. The second width is greater than the first width. An upper level interconnect line is formed on the lower level interconnect line.

Abstract: Techniques to enable bottom barrier free interconnects without voids. In one aspect, a method of forming interconnects includes: forming metal lines embedded in a dielectric; depositing a sacrificial dielectric over the metal lines; patterning vias and trenches in the sacrificial dielectric down to the metal lines, with the trenches positioned over the vias; lining the vias and trenches with a barrier layer; depositing a conductor into the vias and trenches over the barrier layer to form the interconnects; forming a selective capping layer on the interconnects; removing the sacrificial dielectric in its entirety; and depositing an interlayer dielectric (ILD) to replace the sacrificial dielectric. An interconnect structure is also provided.

Abstract: A method for making a semiconductor structure includes forming a metallization layer on a substrate. The method further includes forming a dielectric layer on the metallization layer. The method further includes forming one or more openings in the dielectric layer and the metallization layer exposing a top surface of the substrate. The method further includes forming a polymer-adhering liner layer on sidewalls of the dielectric layer in the one or more openings. The method further includes selectively depositing a dielectric polymer in at least a top portion of the one or more openings and on the polymer-adhering liner layer. The dielectric polymer seals an air gap positioned between a bottom surface of the dielectric polymer and a top surface of the substrate.

Abstract: A method for making a semiconductor structure includes forming a metallization layer on a substrate. The method further includes forming a dielectric layer on the metallization layer. The method further includes forming one or more openings in the dielectric layer and the metallization layer exposing a top surface of the substrate. The method further includes forming a polymer-adhering liner layer on sidewalls of the dielectric layer in the one or more openings. The method further includes selectively depositing a dielectric polymer in at least a top portion of the one or more openings and on the polymer-adhering liner layer. The dielectric polymer seals an air gap positioned between a bottom surface of the dielectric polymer and a top surface of the substrate.

Abstract: A method of fabricating a semiconductor device includes depositing a spacer material in a trench arranged in a dielectric layer. An end of the trench extends to a metal layer of an interconnect structure. A portion of the spacer material in contact with the metal layer is removed. A recess is formed in the metal layer at the end of the trench.