Abstract: Structures including a grating coupler and methods of fabricating a structure including a grating coupler. The structure includes structure includes a dielectric layer on a substrate, a first waveguide core positioned in a first level over the dielectric layer, and a second waveguide core positioned in a second level over the dielectric layer. The second level differs in elevation above the dielectric layer from the first level. The first waveguide core includes a tapered section. The structure further includes a grating coupler having a plurality of segments positioned in the second level adjacent to the second waveguide core. The segments of the grating coupler and the tapered section of the first waveguide core are positioned in an overlapping arrangement.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers integrated with one or more airgap and methods of manufacture. The structure includes: a substrate material comprising one or more airgaps; and a grating coupler disposed over the substrate material and the one or more airgaps.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers integrated with one or more airgap and methods of manufacture. The structure includes: a substrate material comprising one or more airgaps; and a grating coupler disposed over the substrate material and the one or more airgaps.

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The edge coupler includes a waveguide core, and a shaped layer is positioned over a portion of the waveguide core. The waveguide core is comprised of a first material, and the shaped layer is comprised of a second material different in composition from the first material. The first material may be, for example, single-crystal silicon, and the second material may be, for example, silicon nitride.

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The edge coupler includes a waveguide core, and a shaped layer is positioned over a portion of the waveguide core. The waveguide core is comprised of a first material, and the shaped layer is comprised of a second material different in composition from the first material. The first material may be, for example, single-crystal silicon, and the second material may be, for example, silicon nitride.

Abstract: Embodiments of the disclosure provide a demultiplexer for processing a multiplexed optical input. The demultiplexer may include a plurality of Mach-Zehnder Interferometric (MZI) stages for converting the multiplexed optical input into a plurality of component optical signals. Each of the plurality of component optical signals corresponds to a respective wavelength-space component of the multiplexed optical input. A plurality of bandpass filters, each having a respective wavelength passband, may receive one of the plurality of component optical signals. The plurality of bandpass filters generates a plurality of demultiplexed optical signals based on the plurality of component optical signals.

Abstract: Structures that include a Bragg grating and methods of fabricating a structure that includes a Bragg grating. Bragg elements are positioned adjacent to a waveguide. The Bragg elements are separated by grooves that alternate with the Bragg elements. A dielectric layer includes portions positioned to close the grooves to define airgaps. The airgaps are respectively arranged between adjacent pairs of the Bragg elements. The Bragg elements may be used to form the Bragg grating.

Abstract: Structures that include a waveguide and methods of fabricating a structure that includes a waveguide. A tapered feature composed of a dielectric material is arranged over the waveguide. The tapered feature includes a sidewall that is angled relative to a longitudinal axis of the waveguide.

Abstract: Embodiments of the disclosure provide an interconnect structure including: a first die having a first surface and an opposing second surface, and a groove within first surface of the first die; an adhesive dielectric layer mounted to the opposing second surface of the first die; a second die having a first surface mounted to the adhesive dielectric layer, and an opposing second surface, wherein the adhesive dielectric layer is positioned directly between the first and second dies; and a through-semiconductor via (TSV) including a first TSV metal extending from the first surface of the first die to the adhesive dielectric layer, and a second TSV metal substantially aligned with the first TSV metal and extending from the adhesive dielectric layer to the opposing second surface of the second die, wherein the TSV includes a metal-to-metal bonding interface between the first and second TSV metals within the adhesive dielectric layer.

Abstract: An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semiconductor substrate; creating a plurality of voids inside the insulating layer, with the plurality of voids spanning across a predefined area and being substantially confined within a range of depth below a top surface of the insulating layer; creating at least one via hole in the insulating layer, with the via hole passing through the predefined area; and filling the via hole, and the plurality of voids inside the insulating layer through at least the via hole, with a conductive material to form a local metallization. A semiconductor structure having the local metallization is also provided.

Abstract: An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semiconductor substrate; creating a plurality of voids inside the insulating layer, with the plurality of voids spanning across a predefined area and being substantially confined within a range of depth below a top surface of the insulating layer; creating at least one via hole in the insulating layer, with the via hole passing through the predefined area; and filling the via hole, and the plurality of voids inside the insulating layer through at least the via hole, with a conductive material to form a local metallization. A semiconductor structure having the local metallization is also provided.

Abstract: An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semiconductor substrate; creating a plurality of voids inside the insulating layer, with the plurality of voids spanning across a predefined area and being substantially confined within a range of depth below a top surface of the insulating layer; creating at least one via hole in the insulating layer, with the via hole passing through the predefined area; and filling the via hole, and the plurality of voids inside the insulating layer through at least the via hole, with a conductive material to form a local metallization. A semiconductor structure having the local metallization is also provided.

Abstract: Methods for selective salicidation of a semiconductor device. The invention implements a chemical surface pretreatment by immersion in ozonated water H2O prior to metal deposition. The pretreatment forms an interfacial layer that prevents salicidation over an n-type structure. As a result, the invention does not add any additional process steps to the conventional salicidation processing.

Abstract: A method of fabricating a silicon-on-insulator (SOI) having a superficial Si-containing layer that has a reduced number of tile and divot defects is provided. The method includes the steps of: implanting oxygen ions into a surface of a Si-containing substrate, the implanted oxygen ions having a concentration sufficient to form a buried oxide region during a subsequent annealing step; and annealing the substrate containing implanted oxygen ions under conditions wherein the implanted oxygen ions form a buried oxide region which electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. Moreover, the annealing conditions employed are capable of reducing the number of tile or divot defects present in the superficial Si-containing layer so as to allow optical detection of any other defect that has a lower density than the tile or divot defect. The present invention also relates to the SOI substrate that is produced using the inventive method.

Abstract: A method of fabricating a silicon-on-insulator (SOI) having a superficial Si-containing layer that has a reduced number of tile and divot defects is provided. The method includes the steps of: implanting oxygen ions into a surface of a Si-containing substrate, the implanted oxygen ions having a concentration sufficient to form a buried oxide region during a subsequent annealing step; and annealing the substrate containing implanted oxygen ions under conditions wherein the implanted oxygen ions form a buried oxide region which electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. Moreover, the annealing conditions employed are capable of reducing the number of tile or divot defects present in the superficial Si-containing layer so as to allow optical detection of any other defect that has a lower density than the tile or divot defect. The present invention also relates to the SOI substrate that is produced using the inventive method.

Abstract: A novel method for forming substrate contact regions on a SOI substrate without requiring additional space, and in order to provide lower diffusion capacitance. The method utilizes known semiconductor processing techniques. This method for selectively modifying the BOX region of a SOI substrate involves first providing a silicon substrate. Then, ion implanting the base using SIMOX techniques (e.g. O2 implant) is accomplished. Next, the substrate is photopatterned to protect the modified BOX region. Then, further ion implanting using a “touch-up” O2 implant is accomplished, thereby resulting in a good quality BOX as typically practiced. The final step is annealing the substrate. The area of the substrate, which had a mask present, would not receive the “touch-up” O2 implant (second ion implant), which in turn would result in a leaky BOX.

Abstract: A method of improving surface morphology of a semiconductor substrate when using an SOI technique comprises providing a silicon ingot positioned on a support member, orientating the silicon ingot in relation to the support member, and a cutting device, and cutting the silicon ingot along about a (100) crystal plane of the silicon ingot, preferably using a wire saw. This then provides a silicon substrate having an initial surface defining a miscut angle which is less than about 0.15 degrees from the (100) crystal plane. The method then comprises processing the silicon substrate using SIMOX processing, which includes implanting oxygen atoms in the silicon substrate to form a buried oxide layer and annealing the silicon substrate to provide a final substrate surface. Finally, the method includes accepting the final substrate surface for further processing when the final substrate surface measures between 2-20 Å RMS using an atomic force microscopy technique.

Abstract: A method of fabricating a silicon-on-insulator (SOI) having a superficial Si-containing layer that has a reduced number of tile and divot defects is provided. The method includes the steps of: implanting oxygen ions into a surface of a Si-containing substrate, the implanted oxygen ions having a concentration sufficient to form a buried oxide region during a subsequent annealing step; and annealing the substrate containing implanted oxygen ions under conditions wherein the implanted oxygen ions form a buried oxide region which electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. Moreover, the annealing conditions employed are capable of reducing the number of tile or divot defects present in the superficial Si-containing layer so as to allow optical detection of any other defect that has a lower density than the tile or divot defect. The present invention also relates to the SOI substrate that is produced using the inventive method.

Abstract: A method to control the quality of a buried oxide region, and to substantially reduce or eliminate deep divots in SOI substrates is provided. Specifically, the inventive method includes the steps of implanting oxygen ions into a surface of a Si-containing substrate; and annealing the Si-containing substrate containing the implanted oxygen ion at a temperature of about 1300° C. or above and in a chlorine-containing ambient so as to form a buried oxide region that electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. The chlorine-containing ambient employed in the annealing step includes oxygen and a chlorine-containing carrier gas such as HCl, methylene chloride, trichloroethylene and trans 1,2-dichloroethane.

Abstract: A method for preparing a semiconductor material for formation of a silicide layer on selected areas thereupon is disclosed. In an exemplary embodiment of the invention, the method includes removing at least one of a nitride and an oxynitride film from the selected areas, removing metallic particles from the selected areas, removing surface particles from the selected areas, removing organics from the selected areas, and removing an oxide layer from the selected areas.