Patents by Inventor Kenneth P. Snowdon

Kenneth P. Snowdon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10826488
    Abstract: A switch device includes a common node that is connected to end nodes, such as that of computer interface ports. The switch device includes several switch circuits that can be connected in series to form a switch path between the common node and an end node. A switch circuit can include a main switch, such as a transistor that can be configured to withstand a positive or negative voltage surge by automatically changing the connection of its gate.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: November 3, 2020
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Lei Huang, Na Meng, Kenneth P. Snowdon
  • Patent number: 10389169
    Abstract: This document discusses, among other things, an electronic circuit and method for defaulting to a valid battery supply to power an electronic device. In an example, an electronic circuit can be configured to receive information about the battery supply (e.g., an internal battery), such as the battery supply voltage (VBAT), and to determine if the battery supply is valid or invalid using the received information (e.g., comparing the VBAT to a threshold). If VBAT is valid, the electronic device can default to receiving power from the battery supply. If VBAT is invalid, the electronic device can receive power from another power supply, such as an external supply.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: August 20, 2019
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James A. Siulinski, Kenneth P. Snowdon
  • Publication number: 20190207604
    Abstract: A switch device includes a common node that is connected to end nodes, such as that of computer interface ports. The switch device includes several switch circuits that can be connected in series to form a switch path between the common node and an end node. A switch circuit can include a main switch, such as a transistor that can be configured to withstand a positive or negative voltage surge by automatically changing the connection of its gate.
    Type: Application
    Filed: March 12, 2019
    Publication date: July 4, 2019
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Lei HUANG, Na MENG, Kenneth P. SNOWDON
  • Patent number: 10270438
    Abstract: A switch device includes a common node that is connected to end nodes, such as that of computer interface ports. The switch device includes several switch circuits that can be connected in series to form a switch path between the common node and an end node. A switch circuit can include a main switch, such as a transistor that can be configured to withstand a positive or negative voltage surge by automatically changing the connection of its bulk.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: April 23, 2019
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Lei Huang, Na Meng, Kenneth P. Snowdon
  • Patent number: 10190919
    Abstract: In a general aspect, a circuit can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance and a temperature information circuit. The temperature information circuit can be configured to: receive a first voltage from the first terminal of the temperature-sensitive resistance; receive a second voltage from the second terminal of the temperature-sensitive resistance; and provide temperature information based on the first voltage and the second voltage. The temperature information circuit can include a first comparison circuit configured to determine a difference between the first voltage and the second voltage, and a second comparison circuit configured to compare an output of the first comparison circuit to a reference.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: January 29, 2019
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Roy Yarbrough
  • Patent number: 10097084
    Abstract: Systems and methods are disclosed, including, for example, a low-voltage control circuit configured to receive a charge pump voltage, a rail voltage, and a switch control signal, to provide the charge pump voltage when the switch control signal is in a first state, and to provide the higher of the charge pump voltage and the rail voltage when the switch control signal is in a second state. The system can include a first pick-high circuit configured to receive the rail voltage and the charge pump voltage, and to provide the higher of the rail voltage and the charge pump voltage at an output. The switch control signal, in the first state, can include the output of the pick-high circuit. Methods of forming such apparatus are disclosed, as well as methods of operation, and other embodiments.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: October 9, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Julie Lynn Stultz
  • Patent number: 9899370
    Abstract: This document discusses, among other things, an auxiliary self-protecting transistor circuit, system, and method configured to protect a complementary metal-oxide semiconductor (CMOS) transistor. The auxiliary self-protecting transistor circuit can include an ESD device including a gate terminal, a drain terminal, and a source terminal. The ESD device is configured to be coupled to an isolation region of a complementary metal-oxide semiconductor (CMOS) transistor, and can provide a discharge path between the isolation region of the CMOS transistor and the source terminal of the ESD device. The isolation region of the CMOS transistor can include a blocking junction, such as an n-doped isolation well (niso), a p-type well (pwell), or one or more other blocking junctions.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: February 20, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Taeghyun Kang, Alister Young
  • Publication number: 20170350768
    Abstract: In a general aspect, a circuit can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance and a temperature information circuit. The temperature information circuit can be configured to: receive a first voltage from the first terminal of the temperature-sensitive resistance; receive a second voltage from the second terminal of the temperature-sensitive resistance; and provide temperature information based on the first voltage and the second voltage. The temperature information circuit can include a first comparison circuit configured to determine a difference between the first voltage and the second voltage, and a second comparison circuit configured to compare an output of the first comparison circuit to a reference.
    Type: Application
    Filed: August 24, 2017
    Publication date: December 7, 2017
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Kenneth P. SNOWDON, Roy YARBROUGH
  • Patent number: 9838004
    Abstract: Systems and methods are disclosed, including a protection multiplexer circuit configured to receive a control signal and a reference voltage, to provide the reference voltage at an output when the control signal is in a first state, and to isolate the reference voltage from the output when the control signal is in a second state. The protection multiplexer circuit includes cascaded first and second transistors, wherein the first transistor is a native transistor. Control inputs of the first and second transistors are configured to receive the control signal, a first terminal of the first transistor is configured to receive the reference voltage, and the first terminal of the second transistor is coupled to the output. Methods of operation are disclosed, and other embodiments.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: December 5, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Julie Lynn Stultz
  • Patent number: 9812440
    Abstract: This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and method configured to reduce capacitance of an ESD structure with little to no change in other ESD structure parameters. A bulk terminal of an ESD device can be negative biased to reduce a drain terminal to source terminal capacitance of the ESD device. A charge pump can be configured to provide a negative bias to the bulk terminal of the ESD device. In certain examples, the gate terminal of the ESD device can be coupled to the source terminal of the ESD device, such as through a resistor, and the source terminal can be coupled to ground.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: November 7, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Taeghyun Kang, Yongliang Li
  • Patent number: 9772233
    Abstract: This document discusses, among other things, an apparatus and method for providing temperature information. In an example, an integrated circuit apparatus can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance, and a temperature information circuit configured to receive a first voltage from the first terminal of the temperature-sensitive resistance and a second voltage from the second terminal of the temperature-sensitive resistance. The temperature information circuit can provide the temperature information using the first and second voltages.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: September 26, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Roy Yarbrough
  • Publication number: 20160285446
    Abstract: Systems and methods are disclosed, including a protection multiplexer circuit configured to receive a control signal and a reference voltage, to provide the reference voltage at an output when the control signal is in a first state, and to isolate the reference voltage from the output when the control signal is in a second state. The protection multiplexer circuit includes cascaded first and second transistors, wherein the first transistor is a native transistor. Control inputs of the first and second transistors are configured to receive the control signal, a first terminal of the first transistor is configured to receive the reference voltage, and the first terminal of the second transistor is coupled to the output. Methods of operation are disclosed, and other embodiments.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 29, 2016
    Inventors: Kenneth P. Snowdon, Julie Lynn Stultz
  • Publication number: 20160204696
    Abstract: Systems and methods are disclosed, including, for example, a low-voltage control circuit configured to receive a charge pump voltage, a rail voltage, and a switch control signal, to provide the charge pump voltage when the switch control signal is in a first state, and to provide the higher of the charge pump voltage and the rail voltage when the switch control signal is in a second state. The system can include a first pick-high circuit configured to receive the rail voltage and the charge pump voltage, and to provide the higher of the rail voltage and the charge pump voltage at an output. The switch control signal, in the first state, can include the output of the pick-high circuit. Methods of forming such apparatus are disclosed, as well as methods of operation, and other embodiments.
    Type: Application
    Filed: March 24, 2016
    Publication date: July 14, 2016
    Inventors: Kenneth P. Snowdon, Julie Lynn Stultz
  • Publication number: 20160173084
    Abstract: A switch device includes a common node that is connected to end nodes, such as that of computer interface ports. The switch device includes several switch circuits that can be connected in series to form a switch path between the common node and an end node. A switch circuit can include a main switch, such as a transistor that can be configured to withstand a positive or negative voltage surge by automatically changing the connection of its gate.
    Type: Application
    Filed: July 7, 2015
    Publication date: June 16, 2016
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Lei HUANG, Na MENG, Kenneth P. SNOWDON
  • Publication number: 20160164342
    Abstract: This document discusses, among other things, an electronic circuit and method for defaulting to a valid battery supply to power an electronic device. In an example, an electronic circuit can be configured to receive information about the battery supply (e.g., an internal battery), such as the battery supply voltage (VBAT), and to determine if the battery supply is valid or invalid using the received information (e.g., comparing the VBAT to a threshold). If VBAT is valid, the electronic device can default to receiving power from the battery supply. If VBAT is invalid, the electronic device can receive power from another power supply, such as an external supply.
    Type: Application
    Filed: December 7, 2015
    Publication date: June 9, 2016
    Inventors: James A. Siulinski, Kenneth P. Snowdon
  • Publication number: 20160064920
    Abstract: This document discusses, among other things, an auxiliary self-protecting transistor circuit, system, and method configured to protect a complementary metal-oxide semiconductor (CMOS) transistor. The auxiliary self-protecting transistor circuit can include an ESD device including a gate terminal, a drain terminal, and a source terminal. The ESD device is configured to be coupled to an isolation region of a complementary metal-oxide semiconductor (CMOS) transistor, and can provide a discharge path between the isolation region of the CMOS transistor and the source terminal of the ESD device. The isolation region of the CMOS transistor can include a blocking junction, such as an n-doped isolation well (niso), a p-type well (pwell), or one or more other blocking junctions.
    Type: Application
    Filed: August 25, 2015
    Publication date: March 3, 2016
    Inventors: Kenneth P. Snowdon, Taeghuyn Kang, Alister Young
  • Publication number: 20160064374
    Abstract: This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and method configured to reduce capacitance of an ESD structure with little to no change in other ESD structure parameters. A bulk terminal of an ESD device can be negative biased to reduce a drain terminal to source terminal capacitance of the ESD device. A charge pump can be configured to provide a negative bias to the bulk terminal of the ESD device. In certain examples, the gate terminal of the ESD device can be coupled to the source terminal of the ESD device, such as through a resistor, and the source terminal can be coupled to ground.
    Type: Application
    Filed: August 25, 2015
    Publication date: March 3, 2016
    Inventors: Kenneth P. Snowdon, Taeghyun Kang, Yongliang Li
  • Patent number: 9229833
    Abstract: An apparatus comprises a connector configured to receive an electrical contact of an accessory device that is electrically coupled to a resistor of the accessory device, a current source configured to apply a specified current to the resistor to generate a resulting voltage, a comparator configured to receive and compare the resulting voltage to a reference voltage, and a controller configured to store an outcome of the comparison as a bit in a register, to adjust the applied current using the outcome of the comparison, and to determine a resistance value for the resistor using the bit stored in the register.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: January 5, 2016
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Randall Wetzel, Kenneth P. Snowdon, Kenneth O'Brien
  • Patent number: 9224566
    Abstract: Fuse driver circuits, fuse driver testing circuitry, and methods for testing the fuse driver circuits using the testing circuitry are described. In some embodiments, the fuse driver circuit can be made using a fuse, a NMOS transistor, and a PMOS transistor. The drain of the NMOS transistor can be connected to the negative end of the fuse. The source of the NMOS transistor can be connected to ground. The drain of the PMOS transistor can be connected to a positive end of the fuse. The NMOS and PMOS transistors provide enhanced robustness to the fuse driver circuit in both undervoltage and overvoltage conditions. Other embodiments are also described.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: December 29, 2015
    Assignee: Fairchild Semiconductor Coporation
    Inventors: Kenneth P. Snowdon, William Robert Newberry, James Hall, Roy Yarbrough
  • Patent number: 9209651
    Abstract: This document discusses, among other things, an electronic circuit and method for defaulting to a valid battery supply to power an electronic device. In an example, an electronic circuit can be configured to receive information about the battery supply (e.g., an internal battery), such as the battery supply voltage (VBAT), and to determine if the battery supply is valid or invalid using the received information (e.g., comparing the VBAT to a threshold). If VBAT is valid, the electronic device can default to receiving power from the battery supply. If VBAT is invalid, the electronic device can receive power from another power supply, such as an external supply.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: December 8, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James A. Siulinski, Kenneth P. Snowdon