Patents by Inventor Kenneth P. Snowdon

Kenneth P. Snowdon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9202073
    Abstract: This document discusses, among other things, security measures for shielding or protecting data or sensitive signals on an integrated circuit (IC). The systems and methods disclosed herein can allow erasing sensitive data when access is not locked, locking out access to sensitive data during normal operations through both indirect and direct means, and shielding sensitive signals from invasive probing or manipulation.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: December 1, 2015
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Bert Marston, John R. Turner, Michael Smith, Kenneth P. Snowdon, Nathan Charland
  • Patent number: 9020418
    Abstract: In one general aspect, a repeater can include an input terminal configured to be coupled to a first portion of a MIPI signal path. The MIPI signal path being a unidirectional path between a receiver and a transmitter, the input terminal configured to receive a set of signals from the receiver via the MIPI signal path. The repeater can include an output terminal configured to be coupled to a second portion of the MIPI signal path, the first portion of the MIPI signal path and the second portion of the MIPI signal path having a combined distance greater than 30 centimeters.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: April 28, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Robert A Card, Kenneth P Snowdon
  • Patent number: 8981843
    Abstract: This document discusses, among other things, a control circuit, such as a translator circuit, configured to reduce voltage stress of first and second transistors when a first voltage received by the first transistor exceeds a voltage rating of at least one of the first or second transistors.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 17, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Nickole Gagne, Kenneth P. Snowdon
  • Patent number: 8975923
    Abstract: Apparatus and methods for a protective multiplexer, among other things, are provided. In an example, a protective multiplexer circuit can include a first switch that in a first state can be configured to couple an input of a power supply to at least one of first or second signal nodes of a passgate when a first voltage of the at least one of the first or second signal nodes is below a first limit voltage.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: March 10, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Nickole Gagne, Kenneth P. Snowdon
  • Patent number: 8928142
    Abstract: In one general aspect, an apparatus includes a first capacitor defined by a dielectric disposed between a bump metal and a region of a first conductivity type, and a second capacitor in series with the first capacitor and defined by a PN junction including the region of the first conductivity type and a region of a second conductivity type. The region of the first conductivity type can be configured to be coupled to a first node having a first voltage, and the region of the second conductivity type can be configured to be coupled to a second node having a second voltage different than the first voltage.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: January 6, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Kenneth P. Snowdon
  • Publication number: 20140241398
    Abstract: This document discusses, among other things, an apparatus and method for providing temperature information. In an example, an integrated circuit apparatus can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance, and a temperature information circuit configured to receive a first voltage from the first terminal of the temperature-sensitive resistance and a second voltage from the second terminal of the temperature-sensitive resistance. The temperature information circuit can provide the temperature information using the first and second voltages.
    Type: Application
    Filed: May 8, 2014
    Publication date: August 28, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Roy Yarbrough
  • Publication number: 20140239447
    Abstract: In one general aspect, an apparatus includes a first capacitor defined by a dielectric disposed between a bump metal and a region of a first conductivity type, and a second capacitor in series with the first capacitor and defined by a PN junction including the region of the first conductivity type and a region of a second conductivity type. The region of the first conductivity type can be configured to be coupled to a first node having a first voltage, and the region of the second conductivity type can be configured to be coupled to a second node having a second voltage different than the first voltage.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 28, 2014
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventor: Kenneth P. Snowdon
  • Patent number: 8779839
    Abstract: This document discusses, among other things, a signal switch circuit including a first field effect transistor (FET) configured to couple a first node to a second node in an on-state and a charge pump circuit configured to provide a first supply voltage to control the FET, wherein a reference voltage of the charge pump circuit is coupled to a well of the FET to maintain a constant gate to source voltage of the FET during the on-state.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 15, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Kenneth P. Snowdon
  • Publication number: 20140143887
    Abstract: This document discusses, among other things, security measures for shielding or protecting data or sensitive signals on an integrated circuit (IC). The systems and methods disclosed herein can allow erasing sensitive data when access is not locked, locking out access to sensitive data during normal operations through both indirect and direct means, and shielding sensitive signals from invasive probing or manipulation.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 22, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Bert Marston, John R. Turner, Michael Smith, Kenneth P. Snowdon, Nathan Charland
  • Patent number: 8727616
    Abstract: This document discusses, among other things, an apparatus and method for providing temperature information. In an example, an integrated circuit apparatus can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance, and a temperature information circuit configured to receive a first voltage from the first terminal of the temperature-sensitive resistance and a second voltage from the second terminal of the temperature-sensitive resistance. The temperature information circuit can provide the temperature information using the first and second voltages.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: May 20, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Roy Yarbrough
  • Patent number: 8710900
    Abstract: In one general aspect, an apparatus including a first voltage rail, and a second voltage rail. The apparatus includes a first P-type metal-oxide-semiconductor field effect transistor (MOSFET) PMOS device between the first voltage rail and the second voltage rail where the first PMOS device is configured to electrically couple the first voltage rail to the second voltage rail in response to the first PMOS device being activated. The apparatus can also include a second PMOS device configured to provide a charge pump voltage produced by a charge pump device to the second voltage rail in response to the second PMOS device being activated and the first PMOS device being deactivated. The apparatus can also include a pass gate, and a driver circuit coupled to the pass gate and configured to operate based on a voltage of the second voltage rail.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: April 29, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Nickole Gagne, Kenneth P. Snowdon
  • Patent number: 8692621
    Abstract: In one general aspect, an apparatus can include a phase frequency detector configured to produce a plurality of indicators of relative differences between a frequency of a target oscillator signal and a frequency of a reference oscillator signal. The apparatus can also include a pulse generator configured to produce a plurality of pulses based on the plurality of indicators. The plurality of pulses can include a first portion configured to trigger an increase in the frequency of the target oscillator signal and the plurality of pulses including a second portion configured to trigger a decrease in the frequency of the target oscillator signal.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: April 8, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Jeffrey S. Martin
  • Publication number: 20140049861
    Abstract: Apparatus and methods for a protective multiplexer, among other things, are provided. In an example, a protective multiplexer circuit can include a first switch that in a first state can be configured to couple an input of a power supply to at least one of first or second signal nodes of a passgate when a first voltage of the at least one of the first or second signal nodes is below a first limit voltage.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 20, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Nickole Gagne, Kenneth P. Snowdon
  • Patent number: 8624663
    Abstract: In one general aspect, an apparatus can include a complementary switch circuit including a first portion and a second portion, and a first driver circuit coupled to the first portion of the complementary switch circuit. The apparatus can include a positive charge pump device coupled to the first driver, and a second driver circuit coupled to the second portion of the complementary switch circuit. The apparatus can also include a negative charge pump device coupled to the second driver circuit.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: January 7, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Nickole Gagne, Kenneth P Snowdon
  • Patent number: 8610489
    Abstract: This document discloses, among other things, a switch circuit that includes a depletion-mode field-effect transistor (DMFET) having an ON-state and an OFF-state, wherein the DMFET is configured to couple a first node to a second node in the ON-state, and wherein the DMFET is configured to isolate the first node from the second node in the OFF-state, a negative charge pump that is coupled to a gate terminal of the DMFET, the charge pump configured to supply a negative charge pump voltage to the gate terminal of the DMFET, and a negative discriminator coupled to the charge pump, the discriminator configured to compare a first voltage at the first node and a second voltage at the second node and determine the negative charge pump voltage based on the comparison.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: December 17, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Tyler Daigle, Julie Lynn Stultz, Kenneth P. Snowdon
  • Publication number: 20130321070
    Abstract: This document discusses, among other things, a control circuit, such as a translator circuit, configured to reduce voltage stress of first and second transistors when a first voltage received by the first transistor exceeds a voltage rating of at least one of the first or second transistors.
    Type: Application
    Filed: March 11, 2013
    Publication date: December 5, 2013
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Nickole Gagne, Kenneth P. Snowdon
  • Patent number: 8599525
    Abstract: An apparatus comprises an integrated circuit (IC) including an external IC connection, a high impedance circuit, a biasing circuit communicatively coupled to the external IC connection via the high impedance circuit, and an electro-static discharge (ESD) protection circuit coupled to the biasing circuit to form a circuit shunt path leading from the IC external connection to the ESD protection circuit via the high impedance circuit.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: December 3, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Christopher A. Bennett, Kenneth P. Snowdon
  • Publication number: 20130307591
    Abstract: This document discloses, among other things, a switch circuit that includes a depletion-mode field-effect transistor (DMFET) having an ON-state and an OFF-state, wherein the DMFET is configured to couple a first node to a second node in the ON-state, and wherein the DMFET is configured to isolate the first node from the second node in the OFF-state, a negative charge pump that is coupled to a gate terminal of the DMFET, the charge pump configured to supply a negative charge pump voltage to the gate terminal of the DMFET, and a negative discriminator coupled to the charge pump, the discriminator configured to compare a first voltage at the first node and a second voltage at the second node and determine the negative charge pump voltage based on the comparison.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 21, 2013
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Tyler Daigle, Julie Lynn Stultz, Kenneth P. Snowdon
  • Patent number: 8564918
    Abstract: This document discusses methods and apparatus for preventing or reducing sub-threshold pass gate leakage. In an example, an apparatus can include a pass gate configured to electrically couple a first node with a second node in a first state and to electrically isolate the first node from the second node in a second state, control logic configured to control the pass gate, wherein the control logic includes a supply rail, and an over-voltage circuit configured to compare voltages received at a plurality of input nodes and to couple an output to an input node a highest voltage. In an example, the output of over-voltage circuit can be selectively coupled to the supply rail.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: October 22, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Nickole Gagne, Kenneth P. Snowdon
  • Publication number: 20130249621
    Abstract: In one general aspect, an apparatus including a first voltage rail, and a second voltage rail. The apparatus includes a first P-type metal-oxide-semiconductor field effect transistor (MOSFET) PMOS device between the first voltage rail and the second voltage rail where the first PMOS device is configured to electrically couple the first voltage rail to the second voltage rail in response to the first PMOS device being activated. The apparatus can also include a second PMOS device configured to provide a charge pump voltage produced by a charge pump device to the second voltage rail in response to the second PMOS device being activated and the first PMOS device being deactivated. The apparatus can also include a pass gate, and a driver circuit coupled to the pass gate and configured to operate based on a voltage of the second voltage rail.
    Type: Application
    Filed: March 22, 2012
    Publication date: September 26, 2013
    Inventors: Nickole Gagne, Kenneth P. Snowdon