Abstract: Electrostatic discharge (ESD) clamp using output driver. An electrostatic discharge (ESD) protection device for an output driver having a p-channel transistor and n-transistor pair connected between a power supply terminal and ground for driving an input/output pad therefrom. An ESD event detector is provided for detecting an ESD event on the pad. A drive circuit drives the n-channel and p-channel drive transistors in response to receiving a logic control signal to either drive the pad from the supply terminal or to sink the pad to ground. ESD protection logic circuitry is provided to cause both the p-channel and n-channel transistors to turn on when the ESD event detector detects an ESD event, the ESD protection circuitry disposed forward of the drive circuit such that the ESD protection logic circuitry operates independent of the state of the drive circuit.

Abstract: A microcontroller unit (MCU) is disclosed with a stand-alone Real Time Clock (RTC). The MCU includes a processing circuit for receiving digital information and processing said received digital information. A primary clock circuit provides the timing for the processing circuit. A power control circuit controls the power to the processing circuit and the primary clock circuit to control the operation thereof to operate in at least a full power mode drawing a full power level from a supply voltage input and a reduced power mode drawing less than the full power level from the supply voltage input. A stand-alone RTC circuit is also provided, the stand-alone RTC circuit including an RTC clock circuit operating independent of the primary clock circuit. A timer clocked by the RTC clock circuit is operable to increment a stored time value for output therefrom, the RTC clock circuit having a defined time base. An input/output (I/O) device provides access by the processing circuit to the results output by the timer.

Abstract: The control precision of one or more parameters of an integrated circuit (IC), for example the output voltage of a voltage regulator comprised in the IC, may be improved even when using inaccurate components external to the IC. Control of the output voltage, or any parameter, using components external to the IC may include coupling a resistor to the IC and measuring the actual resistance value of the resistor, and based on the measured value, selecting a nominal resistance value from a set of resistance values previously specified by the user. The output voltage, or parameter, may be generated according to the nominal resistance value instead of the actual resistance value, thereby reducing the error that may be incurred due the actual resistance value of the resistor not matching the expected nominal value of the resistor.

Abstract: A cross-bar matrix includes a plurality of matrix cells arranged in rows and columns wherein each row of cells is associated with a signal input and each column of cells is associated with a common signal output. An enable input controls whether at least a portion of the cells couple a signal on the associated common signal input to a signal output associated with a cell or couple an LCD signal to a signal output and exclude control of the at least portion of said plurality of cells by the control input.

Abstract: Method and apparatus for calibration of a low frequency oscillator in a processor based system. A method for calibrating an on-chip non-precision oscillator. An on-chip precision oscillator is provided having a known frequency of operation that is within an acceptable operating tolerance. The on-chip precision oscillator is used as a time base and then the period of the on-chip oscillator is measured as a function of the time base. The difference between the measured frequency of the on-chip non-precision oscillator and a desired operating frequency of the on-chip non-precision oscillator is then determined. After the difference is determined, the frequency of the on-chip non-precision oscillator is adjusted to minimize the determined difference.

Abstract: A circuit for protecting a battery includes an n-well formed within a p substrate. A p-type resistor is formed with in the n well and has a connection to the battery. An n+ ring is also formed in the n well and substantially surrounds the p-type resistor.

Abstract: A power converter including a hardware efficient control loop architecture. Error detection circuitry may generate an error signal based on the difference between a power converter output voltage and a reference voltage. An oversampling ADC may digitize the error signal. The transfer function associated with the ADC may include quantization levels spaced at non-uniform intervals away from a center code. A digital filter may calculate the average of the digitized error signal. A nonlinear requantizer may reduce the number of codes corresponding to the output of the digital filter. A proportional integral derivative (PID) unit may multiply the output of the nonlinear requantizer by PID coefficients to generate a PID duty cycle command, and a gain compensation unit may dynamically adjust the PID coefficients to maintain a constant control loop gain. A noise-shaped truncation unit including a multi-level error-feedback delta sigma modulator may reduce the resolution of the PID duty cycle command.

Abstract: A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.

Abstract: A voltage reference generator is disclosed that includes a current generator for generating a current that is proportional to absolute temperature (PTAT), the current generator having an internal resistance. This provides a PTAT current that is proportional to the resistance and wherein the temperature coefficient of the PTAT current is defined by the resistance. An output node is driven by the current generator with the PTAT current. A stack of serial connected MOS devices is connected between the output voltage and a ground reference voltage. The stack of transistors has a transimpedance associated therewith which has a temperature coefficient that is opposite in polarity to the temperature coefficient of the internal resistance and of a magnitude to provide a voltage on the output node that is substantially stable over temperature.

Abstract: A voltage monitor having a bandgap reference circuit driven by a voltage to be monitored. The bandgap reference circuit produces a voltage and a second voltage that each vary with the voltage to be monitored. The magnitudes of these voltages are compared by an open loop comparator to provide a high speed output state. The output of the voltage monitor can be used to monitor a supply voltage and produce a reset signal to a processor if the supply voltage falls to a magnitude below a specified threshold.

Abstract: A matrix of routing cells forming a cross-bar decoder (310). Signal triplets are coupled through the cross-bar decoder (310) based on control by a microprocessor. A register (50) provide control signals to the cross-bar decoder (310) to either activate or deactivate routing of the triplet signals through cells of the cross-bar decoder (310). The routing cells are arranged in a matrix of columns and rows. Each row of cells is associated with a common data signal input, and each column of the matrix is associated with a common I/O pin. The cells are individually enabled by the microprocessor so that any data signal can be coupled to any of the I/O pins. In addition to routing data signals through the cells, other signals are also routed through the cells.

Abstract: Digital control circuit for switching power supply with pattern generator. A method is disclosed for converting DC power from a first voltage level on an input to a different voltage level on an output for delivery to a load. Current from the input is switched to the output through an inductive element with a plurality of switches, each of the switches driven by a waveform, all of the waveforms driving the switches referenced with a predetermined relationship to a master clock and all operating on a PWM duty cycle of the master clock. The voltage/current parameters on the input and output are measured and then a control algorithm is utilized to determine a change in the PWM duty cycle necessary to make a control move, the control algorithm utilizing as inputs the measured voltage/current parameters. A pre-stored waveform pattern for each of the waveforms is then modified to reflect the change in the PWM duty cycle required for the control move.

Abstract: Serial Data Interface. A method of serial communication is provided with an integrated circuit. The operation of the integrated circuit is first interrupted on at least one input/output associated with the operation of the integrated circuit. Serial data is then transmitted over the at least one input/output, the operation of which was interrupted, and during the interruption thereof.

Abstract: A fractional divide circuit for generating a periodic fractional clock is disclosed. A base clock is provided for generating a pre-divide clock at a base clock frequency with a period counter provided for counting cycles of the base clock. A select register stores constants that define parameters for a fractional divide ratio, there being at least four. A positive edge flip flop is provided wherein two of the constants are associated therewith. A negative edge flip flop is provided wherein the other of the two constants are associated therewith.

Abstract: Clock recovery method for bursty communications. A method is disclosed for recovering the clock from a received data stream that comprising bursts of data with zones of substantially no data between the bursts of data. A receive clock is provided that operates within a reference frequency range. The time between data transitions in the received data is then measuring relative to the receive clock. A determination is then made if the measured time is substantially an integral of the receive clock. If not a substantial integral of the receive clock, the frequency of the receive clock is adjusted to compensate for the difference.

Abstract: Paging scheme for a microcontroller for extending available register space. A method for paging at least a portion of an address space in a processing system is disclosed. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address space of the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein.

Abstract: Method and apparatus for accessing paged memory with indirect addressing. A a method for changing pages of memory in an indirect addressed memory having a plurality of addressable locations therein is diclosed. An index indicative of the page of the memory being addressed is stored in a memory location. The memory is addressed with a direct address that selects one or more of the addressable locations in the addressed page of memory. An interrupt is received from a resource capable of generating an interrupt, which interrupt has associated therewith a defined one of the pages of memory. In response to generation of the interrupt, the value of the stored index t is changed o an index associated with the defined one of the pages of memory associated with the resource. In response to receiving a signal indicative of the generated interrupt having been serviced by a system that services interrupts, the stored index is changed to a different index.

Abstract: A matrix of routing cells forming a cross-bar decoder (70). Signal triplets (84, 86, 88) coupled to the cross-bar decoder (70) are assigned a priority. A register (50) provide outputs to the cross-bar decoder (70) to either activate or deactivate routing of the triplet signals (84, 86,88) through the cross-bar decoder (70). The routing cells (72-82) are arranged in a matrix of columns and rows, where the triplet signals are applied to the row routing cells (72, 74, 76) and are extracted at the column routing cells (76, 80, 82). When a routing cell in a row is enabled to couple signals to an output, it disables all other lower priority routing cells in its column so that they cannot route signals to that output. Based on the automatic disabling of routing cells by others, the signals ripple through the cross-bar decoder (70) until all high priority I/O pins are used.

Abstract: Electrostatic discharge (ESD) clamp using output driver. An electrostatic discharge (ESD) protection device for an output driver having a p-channel transistor and n-transistor pair connected between a power supply terminal and ground for driving an input/output pad therefrom. An ESD event detector is provided for detecting an ESD event on the pad. A drive circuit drives the n-channel and p-channel drive transistors in response to receiving a logic control signal to either drive the pad from the supply terminal or to sink the pad to ground. ESD protection logic circuitry is provided to cause both the p-channel and n-channel transistors to turn on when the ESD event detector detects an ESD event, the ESD protection circuitry disposed forward of the drive circuit such that the ESD protection logic circuitry operates independent of the state of the drive circuit.

Abstract: A voltage monitor having a bandgap reference circuit driven by a voltage to be monitored. The bandgap reference circuit produces a voltage and a second voltage that each vary with the voltage to be monitored. The magnitudes of these voltages are compared by an open loop comparator to provide a high speed output state. The output of the voltage monitor can be used to monitor a supply voltage and produce a reset signal to a processor if the supply voltage falls to a magnitude below a specified threshold.