Abstract: Paging scheme for a microcontroller for extending available register space. A method for paging at least a portion of an address space in a processing system is disclosed. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address space of the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein.

Abstract: Method and apparatus for accessing paged memory with indirect addressing. A a method for changing pages of memory in an indirect addressed memory having a plurality of addressable locations therein is diclosed. An index indicative of the page of the memory being addressed is stored in a memory location. The memory is addressed with a direct address that selects one or more of the addressable locations in the addressed page of memory. An interrupt is received from a resource capable of generating an interrupt, which interrupt has associated therewith a defined one of the pages of memory. In response to generation of the interrupt, the value of the stored index t is changed o an index associated with the defined one of the pages of memory associated with the resource.

Abstract: A matrix of routing cells forming a cross-bar decoder (310). Signal triplets are coupled through the cross-bar decoder (310) based on control by a microprocessor. A register (50) provide control signals to the cross-bar decoder (310) to either activate or deactivate routing of the triplet signals through cells of the cross-bar decoder (310). The routing cells are arranged in a matrix of columns and rows. Each row of cells is associated with a common data signal input, and each column of the matrix is associated with a common I/O pin. The cells are individually enabled by the microprocessor so that any data signal can be coupled to any of the I/O pins. In addition to routing data signals through the cells, other signals are also routed through the cells.

Abstract: Clock recovery method for bursty communications. A method is disclosed for recovering the clock from a received data stream that comprising bursts of data with zones of substantially no data between the bursts of-data. A receive clock is provided that operates within a reference frequency range. The time between data transitions in the received data is then measuring relative to the receive clock. A determination is then made if the measured time is substantially an integral of the receive clock. If not a substantial integral of the receive clock, the frequency of the receive clock is adjusted to compensate for the difference.

Abstract: A precision oscillator for an asynchronous transmission system. An integrated system on a chip with serial asynchronous communication capabilities includes processing circuitry for performing predefined digital processing functions on the chip and having an associated on chip free running clock circuit for generating a temperature compensated clock. An asynchronous on-chip communication device is provided for digitally communicating with an off-chip asynchronous communication device, which off-chip asynchronous communication device has an independent time reference, which communication between the on-chip communication device and the off-chip asynchronous communication device is effected without clock recovery. The asynchronous on-chip communication device has a time-base derived from the temperature compensated clock. The temperature compensated clock provides a time reference for both the processing circuitry and the asynchronous on-chip communication device.

Abstract: A voltage monitor having a bandgap reference circuit driven by a voltage to be monitored. The bandgap reference circuit produces a voltage and a second voltage that each vary with the voltage to be monitored. The magnitudes of these voltages are compared by an open loop comparator to provide a high speed output state. The output of the voltage monitor can be used to monitor a supply voltage and produce a reset signal to a processor if the supply voltage falls to a magnitude below a specified threshold.

Abstract: Serial Data Interface. A method of serial communication is provided with an integrated circuit. The operation of the integrated circuit is first interrupted on at least one input/output associated with the operation of the integrated circuit. Serial data is then transmitted over the at least one input/output, the operation of which was interrupted, and during the interruption thereof.

Abstract: A voltage monitor having a bandgap reference circuit driven by a voltage to be monitored. The bandgap reference circuit produces a voltage and a second voltage that each vary with the voltage to be monitored. The magnitudes of these voltages are compared by an open loop comparator to provide a high speed output state. The output of the voltage monitor can be used to monitor a supply voltage and produce a reset signal to a processor if the supply voltage falls to a magnitude below a specified threshold.

Abstract: A method and apparatus is disclosed for use in an implantable device that communicates with an external device through pulse position modulation. A timing generator is provided as part of the implantable device that determines the phase uncertainty between an external signal and an internal cock signal. The phase uncertainty then is added to the preset delay period to more precisely control the position of the response. The phase uncertainty is measured by a dual slope circuit that varies a state variable (which can be a digital timer, a capacitor voltage, or the like) at a fixed rate with either a positive or negative slope. When the external signal is detected, the stat variable is reset and then decreased at a fixed rate until the next positive edge of the clock signal. The state variable then is increased at the same rate until the subsequent positive clock edge. The resulting variable value is proportional to the phase uncertainty.

Abstract: A method and apparatus is disclosed for an analog-to-digital converter (ADC) to minimize power consumption. The ADC of the present invention minimizes the number of clock cycles required to determine the correct digital code for a particular sample point on an electrogram signal, thus making it possible to turn off some or all of the ADC logic during idle periods. The ADC includes prediction logic that provides a starting point for subsequent digital code representations of the electrogram signal. The prediction logic receives recent code conversions values to predict a current digital code value. This predicted digital code is converted to an analog value and compared with the actual electrogram signal. Next, the ADC adds (or subtracts) a constant value (C) to (or from) the predicted code and compares the result to the electrogram signal.

Abstract: A method and apparatus is disclosed for use in an implantable device that communicates with an external device through pulse position modulation. A timing generator is provided as part of said implantable device that determines the phase uncertainty between an external signal and an internal cock signal. The phase uncertainty then is added to the preset delay period to more precisely control the position of the response. The phase uncertainty is measured by a dual slope circuit that varies a state variable (which can be a digital timer, a capacitor voltage, or the like) at a fixed rate with either a positive or negative slope. When the external signal is detected, the state variable is reset and then decreased at a fixed rate until the next positive edge of the clock signal. The state variable then is increased at the same rate until the subsequent positive clock edge. The resulting variable value is proportional to the phase uncertainty.