Abstract: Various embodiments of the present technology may comprise methods and apparatus for a 3-dimensional capacitive sensor. The method and apparatus may comprise a sensing element formed along multiple planes to create a sensing field. The capacitive sensor comprises at least two parallel sensing planes. Each sensing plane may comprise two electrodes, where one electrode of each sensing plane be configured to operate as a transmission electrode and a reception electrode.

Abstract: Various embodiments of the present technology may comprise methods and apparatus for increased sensitivity of a capacitive proximity sensor. The method and apparatus may comprise additional external capacitors coupled in parallel with internal variable capacitors to increase the effective capacitance of a detection circuit allowing for a larger sensing element, and therefore a stronger sensing field, without increasing the applied voltage or the internal capacitance of the proximity sensor. In alternative embodiments, the methods and apparatus may be configured to operate as one of a transmission electrode and a reception electrode to increase the strength of the sensing field.

Abstract: Various embodiments of the present technology may comprise methods and apparatus for increased sensitivity of a capacitive proximity sensor. The method and apparatus may comprise a sensing element with a plurality of multi-operation electrodes configured to operate as one of a transmission electrode and a reception electrode to increase the strength of the sensing field. Each of the multi-operation electrodes may be selectively operated by a detection circuit to couple one multi-operation electrode to an amplifier and each remaining multi-operation electrode to a voltage source.

Abstract: A production process of acetic acid comprises a reaction step for continuously allowing at least one member selected from the group consisting of methanol, dimethyl ether, and methyl acetate to react with carbon monoxide in a catalyst system comprising a rhodium catalyst, an iodide salt, and methyl iodide in the presence of acetic acid and water in a plant compromising a reactor 1; a flasher 2; and a distillation column 3; wherein part of the vaporized stream is introduced into a heat exchanger 7. The process achieves a production of acetic acid with a high purity in a resource-saving and energy-saving equipment by efficiently removing a reaction heat even in a large-sized plant.

Abstract: A liquid-crystal-driving circuit includes: resistors connected in series between first and second potentials lower than the first potential; one or more voltage follower circuits to impedance-convert one or more intermediate potentials between the first and second potentials, to be outputted, respectively, the intermediate potentials generated at one or more connection points between the resistors, respectively; a common-signal-output circuit to supply common signals to common electrodes of a liquid crystal panel, respectively, the common signals being at the first, second, or one or more intermediate potentials in a predetermined order; and a segment-signal output circuit supplies segment signals to segment electrodes of the liquid crystal panel, respectively, the segment signals being at the first and second potentials, or the intermediate potentials according to the common signals, wherein the segment-signal output circuit increases impedances of the segment signals only for a first period when the of segm

Abstract: A production process of acetic acid comprises a reaction step for continuously allowing at least one member selected from the group consisting of methanol, dimethyl ether, and methyl acetate to react with carbon monoxide in a catalyst system comprising a rhodium catalyst, an iodide salt, and methyl iodide in the presence of acetic acid and water in a plant compromising a reactor 1; a flasher 2; and a distillation column 3; wherein part of the vaporized stream is introduced into a heat exchanger 7. The process achieves a production of acetic acid with a high purity in a resource-saving and energy-saving equipment by efficiently removing a reaction heat even in a large-sized plant.

Abstract: A liquid-crystal-driving circuit includes: resistors connected in series between first and second potentials lower than the first potential; one or more voltage follower circuits to impedance-convert one or more intermediate potentials between the first and second potentials, to be outputted, respectively, the intermediate potentials generated at one or more connection points between the resistors, respectively; a common-signal-output circuit to supply common signals to common electrodes of a liquid crystal panel, respectively, the common signals being at the first, second, or one or more intermediate potentials in a predetermined order; and a segment-signal output circuit supplies segment signals to segment electrodes of the liquid crystal panel, respectively, the segment signals being at the first and second potentials, or the intermediate potentials according to the common signals, wherein the segment-signal output circuit increases impedances of the segment signals only for a first period when the of segm

Abstract: A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.

Abstract: This invention offers an LCD drive circuit that prevents conversion to a wrong duty driving state and an unintended display caused by taking in of serial data corresponding to the wrong duty driving state. The LCD drive circuit is provided with an LCD drive signal generation circuit that generates driving signals to turn LCD segments on and off based on serial data received by a serial data receiving circuit and is switchable between a ¼ duty driving state and a ? duty driving state. The LCD drive circuit is also provided with a driving state setting circuit that sets the LCD drive signal generation circuit to the ¼ duty driving state based on identification data when the serial data receiving circuit receives the serial data corresponding to the ¼ duty driving state and thereafter forbids the LCD drive signal generation circuit to take in serial data corresponding to the ? duty driving state when the serial data receiving circuit receives the serial data corresponding to the ? duty driving state.

Abstract: This invention offers a data communication system that can perform data communication and detection of a data read-in request signal while reducing the number of communication lines to three, and is tolerant of noise. The data communication between a microcomputer and a key scan IC and the detection of the data read-in request signal are performed through a control line, a clock line and a data line. The data communication system is provided with a data line control circuit that controls the data line so that outputting of the data read-in signal RDRQ to the data line is disabled when first command data is inputted to the key scan IC through the data line, and that the outputting of the data read-in request signal RDRQ to the data line is enabled when second command data is inputted from the microcomputer to the key scan IC through the data line.

Abstract: A liquid crystal display drive circuit that suppresses a pulse noise in a liquid crystal display panel without increasing a mounting area is offered. A common signal COMi is varied in a staircase waveform with an increment of 1/3 VLCD in such a way that a high electric potential VLCD?a first intermediate electric potential VLCD1?a second intermediate electric potential VLCD2?a low electric potential VSS, when the common signal COMi varies by the maximum amplitude, in other words, when the common signal COMi makes a transition from the high electric potential VLCD to the low electric potential VSS. The segment signal SEGj is varied similarly in a staircase waveform in such a way that the low electric potential VSS?the second intermediate electric potential VLCD2?the first intermediate electric potential VLCD1?the high electric potential VLCD when the segment signal SEGj makes a transition from the low electric potential VSS to the high electric potential VLCD.

Abstract: A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (<m) bits within a transfer period and a serial clock synchronized therewith, and to shift and hold the serial data by one bit based on the serial clock; an input mode identifying unit to identify whether the input bit number is m or n bits, based on a count value obtained by counting the number of generation of the serial clock during the transfer period; and a parallel data generating unit to output the held m-bit data as first parallel data when the input bit number is identified as m bits, and to output m-bit data obtained by adding predetermined (m?n)-bit data to the held n-bit data as second parallel data when the input bit number is identified as n bits.

Abstract: In a charge pump circuit provided with a positive electric potential generating charge pump circuit that generates a positive electric potential and a negative electric potential generating charge pump circuit that generates a negative electric potential, a parasitic bipolar transistor is prevented from turning on so that the charge pump circuit performs normal voltage boosting operation. First, the negative electric potential generating charge pump circuit is put into operation to generate ?VDD as an output electric potential LV. Since the output electric potential LV is applied to a P-type semiconductor substrate, an electric potential of the P-type semiconductor substrate becomes ?VDD. After that, the positive electric potential generating charge pump circuit is put into operation while the negative electric potential generating charge pump circuit continues its operation.

Abstract: This invention offers an LCD drive circuit that prevents conversion to a wrong duty driving state and an unintended display caused by taking in of serial data corresponding to the wrong duty driving state. The LCD drive circuit is provided with an LCD drive signal generation circuit that generates driving signals to turn LCD segments on and off based on serial data received by a serial data receiving circuit and is switchable between a ¼ duty driving state and a ? duty driving state. The LCD drive circuit is also provided with a driving state setting circuit that sets the LCD drive signal generation circuit to the ¼ duty driving state based on identification data when the serial data receiving circuit receives the serial data corresponding to the ¼ duty driving state and thereafter forbids the LCD drive signal generation circuit to take in serial data corresponding to the ? duty driving state when the serial data receiving circuit receives the serial data corresponding to the ? duty driving state.

Abstract: This invention offers a data communication system that can perform data communication and detection of a data read-in request signal while reducing the number of communication lines to three, and is tolerant of noise. The data communication between a microcomputer and a key scan IC and the detection of the data read-in request signal are performed through a control line, a clock line and a data line. The data communication system is provided with a data line control circuit that controls the data line so that outputting of the data read-in signal RDRQ to the data line is disabled when first command data is inputted to the key scan IC through the data line, and that the outputting of the data read-in request signal RDRQ to the data line is enabled when second command data is inputted from the microcomputer to the key scan IC through the data line.

Abstract: A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (<m) bits within a transfer period and a serial clock synchronized therewith, and to shift and hold the serial data by one bit based on the serial clock; an input mode identifying unit to identify whether the input bit number is m or n bits, based on a count value obtained by counting the number of generation of the serial clock during the transfer period; and a parallel data generating unit to output the held m-bit data as first parallel data when the input bit number is identified as m bits, and to output m-bit data obtained by adding predetermined (m-n)-bit data to the held n-bit data as second parallel data when the input bit number is identified as n bits.

Abstract: In a charge pump circuit provided with a positive electric potential generating charge pump circuit that generates a positive electric potential and a negative electric potential generating charge pump circuit that generates a negative electric potential, a parasitic bipolar transistor is prevented from turning on so that the charge pump circuit performs normal voltage boosting operation. First, the negative electric potential generating charge pump circuit is put into operation to generate ?VDD as an output electric potential LV. Since the output electric potential LV is applied to a P-type semiconductor substrate, an electric potential of the P-type semiconductor substrate becomes ?VDD. After that, the positive electric potential generating charge pump circuit is put into operation while the negative electric potential generating charge pump circuit continues its operation.

Abstract: A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.

Abstract: The ring oscillator circuit with the current mirror type current limit circuit of this invention prevents the malfunction and the halt of the ring oscillator. The ring oscillator is configured with the serially connected CMOS inverters INV1–INV5 where the output of the last CMOS inverter INV5 is fed back to the input of the first CMOS inverter INV1. Also, the current mirror type current limit circuit for controlling the electric current going through the CMOS inverters INV1–INV5 is formed. The first supporting transistor T1 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the power supply voltage Vdd and the second supporting transistor T2 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the ground voltage Vss according to the output of the CMOS inverter INV3 two positions ahead of the last inverter INV5 are also formed.

Abstract: The ring oscillator circuit with the current mirror type current limit circuit of this invention prevents the malfunction and the halt of the ring oscillator. The ring oscillator is configured with the serially connected CMOS inverters INV1-INV5 where the output of the last CMOS inverter INV5 is fed back to the input of the first CMOS inverter INV1. Also, the current mirror type current limit circuit for controlling the electric current going through the CMOS inverters INV1-INV5 is formed. The first supporting transistor T1 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the power supply voltage Vdd and the second supporting transistor T2 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the ground voltage Vss according to the output of the CMOS inverter INV3 two positions ahead of the last inverter INV5 are also formed.