Abstract: In a charge pump circuit provided with a positive electric potential generating charge pump circuit that generates a positive electric potential and a negative electric potential generating charge pump circuit that generates a negative electric potential, a parasitic bipolar transistor is prevented from turning on so that the charge pump circuit performs normal voltage boosting operation. First, the negative electric potential generating charge pump circuit is put into operation to generate ?VDD as an output electric potential LV. Since the output electric potential LV is applied to a P-type semiconductor substrate, an electric potential of the P-type semiconductor substrate becomes ?VDD. After that, the positive electric potential generating charge pump circuit is put into operation while the negative electric potential generating charge pump circuit continues its operation.

Abstract: A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (<m) bits within a transfer period and a serial clock synchronized therewith, and to shift and hold the serial data by one bit based on the serial clock; an input mode identifying unit to identify whether the input bit number is m or n bits, based on a count value obtained by counting the number of generation of the serial clock during the transfer period; and a parallel data generating unit to output the held m-bit data as first parallel data when the input bit number is identified as m bits, and to output m-bit data obtained by adding predetermined (m-n)-bit data to the held n-bit data as second parallel data when the input bit number is identified as n bits.

Abstract: A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.

Abstract: The ring oscillator circuit with the current mirror type current limit circuit of this invention prevents the malfunction and the halt of the ring oscillator. The ring oscillator is configured with the serially connected CMOS inverters INV1–INV5 where the output of the last CMOS inverter INV5 is fed back to the input of the first CMOS inverter INV1. Also, the current mirror type current limit circuit for controlling the electric current going through the CMOS inverters INV1–INV5 is formed. The first supporting transistor T1 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the power supply voltage Vdd and the second supporting transistor T2 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the ground voltage Vss according to the output of the CMOS inverter INV3 two positions ahead of the last inverter INV5 are also formed.

Abstract: The ring oscillator circuit with the current mirror type current limit circuit of this invention prevents the malfunction and the halt of the ring oscillator. The ring oscillator is configured with the serially connected CMOS inverters INV1-INV5 where the output of the last CMOS inverter INV5 is fed back to the input of the first CMOS inverter INV1. Also, the current mirror type current limit circuit for controlling the electric current going through the CMOS inverters INV1-INV5 is formed. The first supporting transistor T1 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the power supply voltage Vdd and the second supporting transistor T2 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the ground voltage Vss according to the output of the CMOS inverter INV3 two positions ahead of the last inverter INV5 are also formed.

Abstract: A plasma addressing display device of the present invention includes: a plasma addressing substrate; a color filter substrate; and a display medium layer interposed between the plasma addressing substrate and the color filter substrate is provided. The plasma addressing substrate includes: a first substrate; a dielectric sheet provided near the display medium layer; a plurality of electrode lines provided at regular intervals on the first substrate; a plurality of partition walls provided respectively on the plurality of electrode lines; and a plurality of strip plasma discharge channels each enclosed by the first substrate, the dielectric sheet and the partition walls. The color filter substrate includes: a second substrate; a color filter layer provided on the second substrate; a plurality of strip electrodes provided on the color filter layer so as to extend in a direction orthogonal to the plurality of strip plasma discharge channels.