Patents by Inventor Kensuke Yamamoto
Kensuke Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11971479Abstract: An ultrasonic sensor is provided with an ultrasonic element that converts between an electrical signal and an ultrasonic vibration and an element accommodating case having a bottomed cylindrical shape and accommodating the ultrasonic element inside thereof. The element accommodating case includes a side plate portion formed in a cylindrical shape that surrounds a directional center axis, and a bottom plate portion that closes one end side of the side plate portion in an axial direction which is parallel to the directional center axis. The ultrasonic element is attached to the bottom plate portion. The bottom plate portion includes at least one protrusion. The protrusions vibrate together with the bottom plate portion when the bottom plate portion vibrates as an ultrasonic vibration.Type: GrantFiled: November 4, 2021Date of Patent: April 30, 2024Assignee: DENSO CORPORATIONInventors: Masayoshi Satake, Youhei Suzuki, Kensuke Kobayashi, Dai Kondo, Syoya Ishida, Yudai Yamamoto, Kenji Fukabori
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Patent number: 11961586Abstract: A semiconductor device according to an embodiment includes: a logic control circuit to which a signal is input; a timing information storage circuit configured to store timing information related to a start timing of correction processing that corrects a duty cycle of the signal; and a sequencer configured to start execution of the correction processing based on the timing information when a command related to the execution of the correction processing is received.Type: GrantFiled: January 18, 2022Date of Patent: April 16, 2024Assignee: Kioxia CorporationInventor: Kensuke Yamamoto
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Publication number: 20240094941Abstract: A semiconductor memory device includes a memory cell storing data; a signal pad inputting write data to the memory cell and from which read data read from the memory cell is output to an external controller; a first control pad receiving a first timing control signal from the external controller; and a second control pad outputting a second timing control signal to the external controller. In a first time period after a data out command is received, dummy data are output from the signal pad while the second timing control signal from the second control pad is toggling in response to toggling of the first timing control signal input to the first control pad. In a second time period after the first time period, read data are output from the signal pad while the second timing control signal is toggling in response to toggling of the first timing control signal.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Applicant: Kioxia CorporationInventor: Kensuke YAMAMOTO
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Patent number: 11876647Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.Type: GrantFiled: July 3, 2022Date of Patent: January 16, 2024Assignee: Kioxia CorporationInventors: Kensuke Yamamoto, Kosuke Yanagidaira
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Patent number: 11868648Abstract: A memory system outputs read enable signals RE and /RE during a period of a standby time tWHR2 necessary for a process of output to a controller, and causes an output, circuit to output dummy data preset in signals DQS and /DQS.Type: GrantFiled: January 14, 2022Date of Patent: January 9, 2024Assignee: Kioxia CorporationInventor: Kensuke Yamamoto
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Publication number: 20230223938Abstract: A device includes a memory cell array configured to store data; and a signal propagation circuit configured to propagate a signal between the memory cell array and a host. The signal propagation circuit includes a first inverted signal output circuit, a second inverted signal output circuit including an input terminal connected to i) an output terminal of the first inverted signal output circuit and ii) an output terminal of the second inverted signal output circuit, a third inverted signal output circuit including an input terminal connected to i) the output terminal of the first inverted signal output circuit and ii) the output terminal of the second inverted signal output circuit, and a fourth inverted signal output circuit including an input terminal connected to i) an output terminal of the third inverted signal output circuit and ii) an output terminal of the fourth inverted signal output circuit.Type: ApplicationFiled: March 22, 2023Publication date: July 13, 2023Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kensuke YAMAMOTO, Ryo FUKUDA, Masaru KOYANAGI, Kenro KUBOTA, Masato DOME
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Patent number: 11637555Abstract: A semiconductor memory device includes a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal. The signal propagation circuit includes a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit, and further including a terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.Type: GrantFiled: January 31, 2022Date of Patent: April 25, 2023Assignee: Kioxia CorporationInventors: Junya Matsuno, Kensuke Yamamoto, Ryo Fukuda, Masaru Koyanagi, Kenro Kubota, Masato Dome
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Publication number: 20230070380Abstract: A semiconductor device according to an embodiment includes: a logic control circuit to which a signal is input; a timing information storage circuit configured to store timing information related to a start timing of correction processing that corrects a duty cycle of the signal; and a sequencer configured to start execution of the correction processing based on the timing information when a command related to the execution of the correction processing is received.Type: ApplicationFiled: January 18, 2022Publication date: March 9, 2023Applicant: Kioxia CorporationInventor: Kensuke YAMAMOTO
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Patent number: 11568935Abstract: A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.Type: GrantFiled: May 25, 2021Date of Patent: January 31, 2023Assignee: Kioxia CorporationInventors: Kazuhiko Satou, Ryo Fukuda, Masaru Koyanagi, Kensuke Yamamoto, Masato Dome, Kei Shiraishi, Junya Matsuno, Kenro Kubota
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Publication number: 20230028971Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.Type: ApplicationFiled: October 3, 2022Publication date: January 26, 2023Applicant: Kioxia CorporationInventors: Masato DOME, Kensuke YAMAMOTO, Masaru KOYANAGI, Ryo FUKUDA, Junya MATSUNO, Kenro KUBOTA
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Publication number: 20230018613Abstract: A semiconductor device includes a first circuit configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level, the first voltage being higher than the second voltage. A second circuit is coupled to the first node and is configured to latch data based on a voltage of the first node; and a third circuit is coupled to the first node and is configured to output a third voltage to the first node while the first circuit is outputting the first voltage to the first node, and to output a fourth voltage to the first node while the first circuit is outputting the second voltage to the first node, the third voltage being lower than the first voltage, and the fourth voltage being higher than the second voltage.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kenro KUBOTA, Masato DOME, Kensuke YAMAMOTO, Kei SHIRAISHI, Kazuhiko SATOU, Ryo FUKUDA, Masaru KOYANAGI
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Patent number: 11495308Abstract: According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.Type: GrantFiled: March 16, 2021Date of Patent: November 8, 2022Assignee: KIOXIA CORPORATIONInventors: Junya Matsuno, Kenro Kubota, Masato Dome, Kensuke Yamamoto, Kei Shiraishi, Kazuhiko Satou, Ryo Fukuda, Masaru Koyanagi
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Patent number: 11495307Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.Type: GrantFiled: March 16, 2021Date of Patent: November 8, 2022Assignee: KIOXIA CORPORATIONInventors: Masato Dome, Kensuke Yamamoto, Masaru Koyanagi, Ryo Fukuda, Junya Matsuno, Kenro Kubota
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Publication number: 20220337457Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.Type: ApplicationFiled: July 3, 2022Publication date: October 20, 2022Inventors: Kensuke YAMAMOTO, Kosuke YANAGIDAIRA
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Patent number: 11447178Abstract: A towing assist device includes a controller configured to assist reversing of a vehicle to which a trailer is coupled with a coupling tool, and a monitor configured to display a periphery of the coupling tool attached to a rear portion of the vehicle with a rear view at least when the vehicle reverses, wherein the controller includes an alarm angle calculator configured to calculate an alarm angle equal to or smaller than a jackknife angle causing a jackknife phenomenon by the vehicle and the trailer in reversing, and an alarm generator configured to give an alarm when a trailer angle between the vehicle and the trailer is equal to or larger than the alarm angle.Type: GrantFiled: December 3, 2020Date of Patent: September 20, 2022Assignee: CLARION CO., LTD.Inventors: Kensuke Yamamoto, Ryo Sakurai
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Patent number: 11381425Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.Type: GrantFiled: December 17, 2020Date of Patent: July 5, 2022Assignee: KIOXIA CORPORATIONInventors: Kensuke Yamamoto, Kosuke Yanagidaira
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Patent number: 11380406Abstract: In general, according to one embodiment, an output circuit includes first to third power supply lines, a pad, first to second transistors, and a first circuit. A first end of the first transistor is coupled to the first power supply line. A second end of the first transistor is coupled to the pad. A first end of the second transistor is coupled to the second power supply line. A second end of the second transistor is coupled to the pad. The first circuit is coupled to each of the third power supply line and a gate of the first transistor. In a first case, the first circuit applies a fourth voltage to the gate of the first transistor.Type: GrantFiled: September 11, 2020Date of Patent: July 5, 2022Assignee: KIOXIA CORPORATIONInventors: Yousuke Hagiwara, Kensuke Yamamoto, Takeshi Hioka, Satoshi Inoue
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Publication number: 20220158639Abstract: A semiconductor memory device includes a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal. The signal propagation circuit includes a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit, and further including a terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kensuke YAMAMOTO, Ryo FUKUDA, Masaru KOYANAGI, Kenro KUBOTA, Masato DOME
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Publication number: 20220137870Abstract: A memory system outputs read enable signals RE and /RE during a period of a standby time tWHR2 necessary for a process of output to a controller, and causes an output, circuit to output dummy data preset in signals DQS and /DQS.Type: ApplicationFiled: January 14, 2022Publication date: May 5, 2022Applicant: Kioxia CorporationInventor: Kensuke YAMAMOTO
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Publication number: 20220093185Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.Type: ApplicationFiled: March 16, 2021Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Masato DOME, Kensuke YAMAMOTO, Masaru KOYANAGI, Ryo FUKUDA, Junya MATSUNO, Kenro KUBOTA