Patents by Inventor Kensuke Yamamoto
Kensuke Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220093185Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.Type: ApplicationFiled: March 16, 2021Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Masato DOME, Kensuke YAMAMOTO, Masaru KOYANAGI, Ryo FUKUDA, Junya MATSUNO, Kenro KUBOTA
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Publication number: 20220093188Abstract: According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.Type: ApplicationFiled: March 16, 2021Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kenro KUBOTA, Masato DOME, Kensuke YAMAMOTO, Kei SHIRAISHI, Kazuhiko SATOU, Ryo FUKUDA, Masaru KOYANAGI
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Patent number: 11277134Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal, wherein the signal propagation circuit includes: a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit; and a fifth inverted signal output circuit including an input terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.Type: GrantFiled: August 26, 2020Date of Patent: March 15, 2022Assignee: KlOXIA CORPORATIONInventors: Junya Matsuno, Kensuke Yamamoto, Ryo Fukuda, Masaru Koyanagi, Kenro Kubota, Masato Dome
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Publication number: 20220059165Abstract: A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.Type: ApplicationFiled: May 25, 2021Publication date: February 24, 2022Applicant: Kioxia CorporationInventors: Kazuhiko SATOU, Ryo FUKUDA, Masaru KOYANAGI, Kensuke YAMAMOTO, Masato DOME, Kei SHIRAISHI, Junya MATSUNO, Kenro KUBOTA
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Patent number: 11232051Abstract: A non-volatile semiconductor memory device including: a first pad transmitting/receiving a data signal transmitted via a first signal line to/from a memory controller; a second pad transmitting/receiving a strobe signal transmitted via a second signal line to/from the memory controller, the strobe signal specifying a timing of transmitting/receiving the data signal; and a third pad receiving an output instruction signal via a third signal line from the memory controller, the output instruction signal instructing a transmission of the data signal; wherein the non-volatile semiconductor memory device outputs the data signal from the first pad to the memory controller, outputs the strobe signal from the second pad to the memory controller, performs a first calibration operation calibrating the data signal, and performs a second calibration operation calibrating the strobe signal, based on a toggle timing of the strobe signal associated with the output instruction signal.Type: GrantFiled: August 21, 2020Date of Patent: January 25, 2022Assignee: Kioxia CorporationInventors: Kensuke Yamamoto, Masaru Koyanagi, Ryo Fukuda, Junya Matsuno, Kenro Kubota, Masato Dome
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Patent number: 11177008Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.Type: GrantFiled: June 8, 2020Date of Patent: November 16, 2021Assignee: KIOXIA CORPORATIONInventors: Kensuke Yamamoto, Fumiya Watanabe, Shouichi Ozaki
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Publication number: 20210297430Abstract: A vehicle control apparatus includes: a steering control unit connected to an in-vehicle communication network mounted on a vehicle and configured to control a steering motor configured to add an auxiliary torque corresponding to a steering operation by a driver to a steering mechanism; and an illegal signal detection unit connected to the in-vehicle communication network and configured to detect an illegal signal input to the in-vehicle communication network. The steering control unit restricts the auxiliary torque when the illegal signal is detected by the illegal signal detection unit.Type: ApplicationFiled: March 15, 2021Publication date: September 23, 2021Inventors: Ryosuke Oguchi, Yoshiyuki Amanuma, Kensuke Yamamoto, Ryoji Nishimoto, Kazuki Sakuma
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Publication number: 20210271615Abstract: A non-volatile semiconductor memory device including: a first pad transmitting/receiving a data signal transmitted via a first signal line to/from a memory controller; a second pad transmitting/receiving a strobe signal transmitted via a second signal line to/from the memory controller, the strobe signal specifying a timing of transmitting/receiving the data signal; and a third pad receiving an output instruction signal via a third signal line from the memory controller, the output instruction signal instructing a transmission of the data signal; wherein the non-volatile semiconductor memory device outputs the data signal from the first pad to the memory controller, outputs the strobe signal from the second pad to the memory controller, performs a first calibration operation calibrating the data signal, and performs a second calibration operation calibrating the strobe signal, based on a toggle timing of the strobe signal associated with the output instruction signal.Type: ApplicationFiled: August 21, 2020Publication date: September 2, 2021Applicant: Kioxia CorporationInventors: Kensuke YAMAMOTO, Masaru KOYANAGI, Ryo FUKUDA, Junya MATSUNO, Kenro KUBOTA, Masato DOME
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Publication number: 20210273956Abstract: An illegal signal detection apparatus includes: CPU and memory. The CPU is configured to perform: reading normal signal input to communication network at first cycle and abnormal signal input to the communication network at second cycle shorter than the first cycle; counting number of the abnormal signal read in the reading; and determining whether count value corresponding to the number of the abnormal signal read in the reading is equal to or greater than predetermined threshold value when abnormal state in which the abnormal signal is read in predetermined unit time period continuously occurs for predetermined time period. The CPU is configured to perform: the counting including weighting the count value so that the count value increases as compared with the number of the abnormal signal read in the reading with increase in the number of the abnormal signal read in the reading.Type: ApplicationFiled: February 18, 2021Publication date: September 2, 2021Inventors: Ryoji Nishimoto, Hirotomi Nemoto, Kensuke Yamamoto
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Publication number: 20210226632Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal, wherein the signal propagation circuit includes: a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit; and a fifth inverted signal output circuit including an input terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.Type: ApplicationFiled: August 26, 2020Publication date: July 22, 2021Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kensuke YAMAMOTO, Ryo FUKUDA, Masaru KOYANAGI, Kenro KUBOTA, Masato DOME
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Publication number: 20210171099Abstract: A towing assist device includes a controller configured to assist reversing of a vehicle to which a trailer is coupled with a coupling tool, and a monitor configured to display a periphery of the coupling tool attached to a rear portion of the vehicle with a rear view at least when the vehicle reverses, wherein the controller includes an alarm angle calculator configured to calculate an alarm angle equal to or smaller than a jackknife angle causing a jackknife phenomenon by the vehicle and the trailer in reversing, and an alarm generator configured to give an alarm when a trailer angle between the vehicle and the trailer is equal to or larger than the alarm angle.Type: ApplicationFiled: December 3, 2020Publication date: June 10, 2021Inventors: Kensuke YAMAMOTO, Ryo SAKURAI
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Publication number: 20210174882Abstract: In general, according to one embodiment, an output circuit includes first to third power supply lines, a pad, first to second transistors, and a first circuit. A first end of the first transistor is coupled to the first power supply line. A second end of the first transistor is coupled to the pad. A first end of the second transistor is coupled to the second power supply line. A second end of the second transistor is coupled to the pad. The first circuit is coupled to each of the third power supply line and a gate of the first transistor. In a first case, the first circuit applies a fourth voltage to the gate of the first transistor.Type: ApplicationFiled: September 11, 2020Publication date: June 10, 2021Applicant: Kioxia CorporationInventors: Yousuke HAGIWARA, Kensuke YAMAMOTO, Takeshi HIOKA, Satoshi INOUE
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Patent number: 11004521Abstract: A semiconductor device includes pads for inputting and outputting data, a plurality of control circuit groups connected to the pads, a first supply line for supplying a first electric potential to the control circuit groups, and a second supply line for supplying a second electric potential lower than the first electric potential to the control circuit groups. At least one of the first electric potential supply line or the second supply line is provided with a blocking region such that the blocking region prevents supply of the first electric potential, and the first electric potential is supplied to the plurality of control circuit groups from the first supply line divided by the blocking region, or the blocking region prevents supply of the second electric potential, and the second electric potential is supplied to the plurality of control circuit groups from the second supply line divided by the blocking region.Type: GrantFiled: March 3, 2020Date of Patent: May 11, 2021Assignee: KIOXIA CORPORATIONInventors: Yasuhiro Suematsu, Masaru Koyanagi, Kensuke Yamamoto, Ryo Fukuda
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Publication number: 20210105158Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.Type: ApplicationFiled: December 17, 2020Publication date: April 8, 2021Inventors: Kensuke YAMAMOTO, Kosuke YANAGIDAIRA
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Publication number: 20210082525Abstract: A semiconductor device includes pads for inputting and outputting data, a plurality of control circuit groups connected to the pads, a first supply line for supplying a first electric potential to the control circuit groups, and a second supply line for supplying a second electric potential lower than the first electric potential to the control circuit groups. At least one of the first electric potential supply line or the second supply line is provided with a blocking region such that the blocking region prevents supply of the first electric potential, and the first electric potential is supplied to the plurality of control circuit groups from the first supply line divided by the blocking region, or the blocking region prevents supply of the second electric potential, and the second electric potential is supplied to the plurality of control circuit groups from the second supply line divided by the blocking region.Type: ApplicationFiled: March 3, 2020Publication date: March 18, 2021Applicant: KIOXIA CORPORATIONInventors: Yasuhiro SUEMATSU, Masaru KOYANAGI, Kensuke YAMAMOTO, Ryo FUKUDA
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Patent number: 10916276Abstract: According to one embodiment, a nonvolatile memory includes a memory cell array including a first storage region and a second storage region, an input/output circuit configured to communicate with a memory controller, and a control circuit. The control circuit is configured to, upon receiving a first command from the memory controller, execute a first training operation related to the input/output circuit, and upon receiving a second command from the memory controller, store a first result of the first training operation in the first storage region.Type: GrantFiled: February 20, 2019Date of Patent: February 9, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kensuke Yamamoto, Kosuke Yanagidaira, Fumiya Watanabe, Shouichi Ozaki
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Patent number: 10873483Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.Type: GrantFiled: October 1, 2019Date of Patent: December 22, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kensuke Yamamoto, Kosuke Yanagidaira
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Patent number: 10847232Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.Type: GrantFiled: August 29, 2019Date of Patent: November 24, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kei Shiraishi, Masaru Koyanagi, Mikihiko Ito, Yumi Takada, Yasuhiro Hirashima, Satoshi Inoue, Kensuke Yamamoto, Shouichi Ozaki, Taichi Wakui, Fumiya Watanabe
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Publication number: 20200303021Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.Type: ApplicationFiled: June 8, 2020Publication date: September 24, 2020Inventors: Kensuke YAMAMOTO, Fumiya WATANABE, Shouichi OZAKI
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Patent number: 10720221Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.Type: GrantFiled: September 2, 2018Date of Patent: July 21, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kensuke Yamamoto, Fumiya Watanabe, Shouichi Ozaki