Patents by Inventor Kenta Ogawa

Kenta Ogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11447394
    Abstract: Provided is a novel compound which can be used for positive-electrode catalysts of metal-air batteries. The melilite-type complex oxide according to the present invention is represented by a general formula (BazSr1?z)2CoxFe2?2x(SiyGe1?y)1+xO7 (in the formula, 0?x?1, 0?y?1, and 0?z?1, excluding the case where x=1, y=1, and z=0, the case where x=1, y=1, and z=1, the case where x=1, y=0, and z=0, the case where x=1, y=0, and z=1, the case where x=0, y=0, and z=0, and the case where x=0, y=0, and z=1).
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: September 20, 2022
    Assignee: KANAGAWA UNIVERSITY
    Inventors: Satoshi Ogawa, Teruki Motohashi, Saito Miwa, Kenta Suzuki
  • Patent number: 11266904
    Abstract: At least one memory device of a game system stores a plurality of instructions, which, when executed by at least one processor, cause the at least one processor to: set, on a touch panel, a reception area for receiving a direction designation operation; move, in accordance with a movement of a touch position on the touch panel, an operation position in a direction corresponding to a moving direction of the touch position by a distance longer than a moving distance of the touch position; acquire a designated direction based on a direction from a reference position corresponding to the reception area to the operation position; and execute game processing based on the designated direction.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: March 8, 2022
    Assignee: KONAMI DIGITAL ENTERTAINMENT CO., LTD.
    Inventors: Masaki Nakamura, Yugo Kishino, Yuji Fujishiro, Kenta Ogawa, Hideki Yanagihara, Kei Masuda, Junichi Taya, Hideto Nishiyama, Taku Hamasaki
  • Patent number: 11193787
    Abstract: A graph generating device is provided, which may include an interface (an obstacle data acquiring module) and processing circuitry (a first graph generating module, a second graph generating module, and a graph synthesizing module). The interface (the obstacle data acquiring module) may acquire obstacle data including information on an obstacle. The processing circuitry is configured to generate a first graph having an area including the obstacle that is recursively divided with a quadtree splitting method into cells that are exclusive of the obstacle, the first graph has a first vertex set in each cell and adjacent first vertexes being interconnected, to generate a second graph that includes second vertexes interconnected by a different method from the quadtree splitting method, and to generate a combined graph from the first graph and the second graph.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: December 7, 2021
    Assignee: FURUNO ELECTRIC CO., LTD.
    Inventor: Kenta Ogawa
  • Patent number: 10857461
    Abstract: At least one processor of a game control device is configured to: acquire a movement direction of the touch position, when a touch position moves under a state in which a touch panel is being touched; execute first game processing based on the movement direction; detect that the movement direction has changed to any movement direction having an angle of a predetermined angle or more with respect to a movement direction acquired at a predetermined timing; and execute second game processing based on one of the movement direction before the change and the movement direction after the change, when the change in the movement direction is detected.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: December 8, 2020
    Assignee: KONAMI DIGITAL ENTERTAINMENT CO., LTD.
    Inventors: Masaki Nakamura, Yuji Fujishiro, Kenta Ogawa, Yugo Kishino, Kei Masuda, Junichi Taya, Hideto Nishiyama, Taku Hamasaki
  • Patent number: 10773154
    Abstract: At least one processor of a game control device is configured to: display an object on a display region, in a game in which the object is moved in accordance with an operation of a user on a touch panel; set a first region of the display region as an operation region; move the object based on the operation of the user on the operation region; and change the operation region to a second region, in which the object is prevented from being arranged at an edge portion of the second region, in a predetermined game situation, which is one of a situation in which at least a part of the object is outside the first region and a situation in which the object is arranged at an edge portion of the first region.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: September 15, 2020
    Assignee: KONAMI DIGITAL ENTERTAINMENT CO., LTD.
    Inventors: Masaki Nakamura, Yuji Fujishiro, Kenta Ogawa, Yugo Kishino, Kei Masuda, Junichi Taya, Hideto Nishiyama, Taku Hamasaki
  • Publication number: 20200038746
    Abstract: At least one memory device of a game system stores a plurality of instructions, which, when executed by at least one processor, cause the at least one processor to: set, on a touch panel, a reception area for receiving a direction designation operation; move, in accordance with a movement of a touch position on the touch panel, an operation position in a direction corresponding to a moving direction of the touch position by a distance longer than a moving distance of the touch position; acquire a designated direction based on a direction from a reference position corresponding to the reception area to the operation position; and execute game processing based on the designated direction.
    Type: Application
    Filed: September 26, 2019
    Publication date: February 6, 2020
    Inventors: Masaki NAKAMURA, Yugo KISHINO, Yuji FUJISHIRO, Kenta OGAWA, Hideki YANAGIHARA, Kei MASUDA, Junichi TAYA, Hideto NISHIYAMA, Taku HAMASAKI
  • Publication number: 20200018601
    Abstract: A navigation device is provided, which may include an acquiring module and a route creating module. The acquiring module may acquire at least a departing location, a destination location and nautical chart information to be used for creating a traveling route for a ship. When a given navigable area is divided into a first navigable area and a second navigable area based on a given condition, the route creating module may create a route being shorter in total distance and taking priority in passing the first navigable area than the second navigable area, based on the departing location, the destination location, and the nautical chart information.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 16, 2020
    Applicant: Furuno Electric Co., Ltd.
    Inventors: Jun YAMABAYASHI, Kenta OGAWA
  • Publication number: 20200018615
    Abstract: A graph generating device is provided, which may include an interface (an obstacle data acquiring module) and processing circuitry (a first graph generating module, a second graph generating module, and a graph synthesizing module). The interface (the obstacle data acquiring module) may acquire obstacle data including information on an obstacle. The processing circuitry is configured to generate a first graph having an area including the obstacle that is recursively divided with a quadtree splitting method into cells that are exclusive of the obstacle, the first graph has a first vertex set in each cell and adjacent first vertexes being interconnected, to generate a second graph that includes second vertexes interconnected by a different method from the quadtree splitting method, and to generate a combined graph from the first graph and the second graph.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 16, 2020
    Applicant: Furuno Electric Co., Ltd.
    Inventor: Kenta OGAWA
  • Publication number: 20190262709
    Abstract: At least one processor of a game control device is configured to: acquire a movement direction of the touch position, when a touch position moves under a state in which a touch panel is being touched; execute first game processing based on the movement direction; detect that the movement direction has changed to any movement direction having an angle of a predetermined angle or more with respect to a movement direction acquired at a predetermined timing; and execute second game processing based on one of the movement direction before the change and the movement direction after the change, when the change in the movement direction is detected.
    Type: Application
    Filed: May 15, 2019
    Publication date: August 29, 2019
    Inventors: Masaki NAKAMURA, Yuji FUJISHIRO, Kenta OGAWA, Yugo KISHINO, Kei MASUDA, Junichi TAYA, Hideto NISHIYAMA, Taku HAMASAKI
  • Publication number: 20190262700
    Abstract: At least one processor of a game control device is configured to: display an object on a display region, in a game in which the object is moved in accordance with an operation of a user on a touch panel; set a first region of the display region as an operation region; move the object based on the operation of the user on the operation region; and change the operation region to a second region, in which the object is prevented from being arranged at an edge portion of the second region, in a predetermined game situation, which is one of a situation in which at least a part of the object is outside the first region and a situation in which the object is arranged at an edge portion of the first region.
    Type: Application
    Filed: May 15, 2019
    Publication date: August 29, 2019
    Inventors: Masaki NAKAMURA, Yuji FUJISHIRO, Kenta OGAWA, Yugo KISHINO, Kei MASUDA, Junichi TAYA, Hideto NISHIYAMA, Taku HAMASAKI
  • Patent number: 9666659
    Abstract: An external storage device including an interconnect substrate having a contact type external terminal, at least one semiconductor chip disposed over a first surface of the interconnect substrate, and a sealing resin layer which seals the at least one semiconductor chip and does not cover the external terminal. The at least one semiconductor chip includes a storage device, an inductor being connected to the storage device, a driver circuit configured to control the inductor and an interconnect layer. The interconnect layer is formed at a first surface of the semiconductor chip and includes the inductor. The first surface of the semiconductor chip is other than facing the first surface of the interconnect substrate, and the inductor and the driver circuit are connected to each other through the interconnect layer.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 30, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka Nakashiba, Kenta Ogawa
  • Patent number: 9362263
    Abstract: This invention can reduce heat that is generated in a first semiconductor chip and transfers to a second semiconductor chip through through-silicon vias. The first semiconductor chip has the first through-silicon vias. Each of the first through-silicon vias is arranged on any of grid points arranged in m rows and n columns (m>n). The first semiconductor chip also has a first circuit formation area. A first circuit is formed in the first circuit formation area. The first circuit performs signal processing while communicating with the second semiconductor chip. In plan view, the first circuit formation area does not overlap with a through-silicon via area that is defined by coupling the outermost grid points arranged in m rows and n columns. In plan view, some of connection terminals are located between the first circuit formation area and the through-silicon via area.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: June 7, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shintaro Yamamichi, Kenta Ogawa
  • Publication number: 20160005727
    Abstract: This invention can reduce heat that is generated in a first semiconductor chip and transfers to a second semiconductor chip through through-silicon vias. The first semiconductor chip has the first through-silicon vias. Each of the first through-silicon vias is arranged on any of grid points arranged in m rows and n columns (m>n). The first semiconductor chip also has a first circuit formation area. A first circuit is formed in the first circuit formation area. The first circuit performs signal processing while communicating with the second semiconductor chip. In plan view, the first circuit formation area does not overlap with a through-silicon via area that is defined by coupling the outermost grid points arranged in m rows and n columns. In plan view, some of connection terminals are located between the first circuit formation area and the through-silicon via area.
    Type: Application
    Filed: September 11, 2015
    Publication date: January 7, 2016
    Inventors: Shintaro YAMAMACHI, Kenta OGAWA
  • Patent number: 9165879
    Abstract: This invention can reduce heat that is generated in a first semiconductor chip and transfers, to a second semiconductor chip through through-silicon vias. The first semiconductor chip has the first through-silicon vias. Each of the first through-silicon vias is arranged on any of grid points arranged in m rows and n columns (m>n). The first semiconductor chip also has a first circuit formation area. A first circuit is formed in the first circuit formation area. The first circuit performs signal processing while communicating with the second semiconductor chip. In plan view, the first circuit formation area does not overlap with a through-silicon via area that is defined by coupling the outermost grid points arranged in m rows and n columns. In plan view, some of connection terminals are located between the first circuit formation area and the through-silicon via area.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: October 20, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Shintaro Yamamichi, Kenta Ogawa
  • Publication number: 20140361411
    Abstract: This invention can reduce heat that is generated in a first semiconductor chip and transfers, to a second semiconductor chip through through-silicon vias. The first semiconductor chip has the first through-silicon vias. Each of the first through-silicon vias is arranged on any of grid points arranged in m rows and n columns (m>n). The first semiconductor chip also has a first circuit formation area. A first circuit is formed in the first circuit formation area. The first circuit performs signal processing while communicating with the second semiconductor chip. In plan view, the first circuit formation area does not overlap with a through-silicon via area that is defined by coupling the outermost grid points arranged in m rows and n columns. In plan view, some of connection terminals are located between the first circuit formation area and the through-silicon via area.
    Type: Application
    Filed: May 22, 2014
    Publication date: December 11, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Shintaro Yamamichi, Kenta Ogawa
  • Patent number: 8810021
    Abstract: A semiconductor device, includes a substrate with a first surface, a semiconductor chip disposed over the first surface of the substrate, the semiconductor chip including a first region and a second region, and an encapsulant resin formed over the first surface of the substrate and encapsulating the semiconductor chip. The encapsulant resin has a thickness that is less at the first region of the semiconductor chip than that at the second region.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: August 19, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yasutaka Nakashiba, Kenta Ogawa
  • Publication number: 20140191363
    Abstract: An external storage device including an interconnect substrate having a contact type external terminal, at least one semiconductor chip disposed over a first surface of the interconnect substrate, and a sealing resin layer which seals the at least one semiconductor chip and does not cover the external terminal. The at least one semiconductor chip includes a storage device, an inductor being connected to the storage device, a driver circuit configured to control the inductor and an interconnect layer. The interconnect layer is formed at a first surface of the semiconductor chip and includes the inductor. The first surface of the semiconductor chip is other than facing the first surface of the interconnect substrate, and the inductor and the driver circuit are connected to each other through the interconnect layer.
    Type: Application
    Filed: March 10, 2014
    Publication date: July 10, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka Nakashiba, Kenta Ogawa
  • Patent number: 8772914
    Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: July 8, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yasutaka Nakashiba, Kenta Ogawa
  • Patent number: 8753922
    Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: June 17, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yasutaka Nakashiba, Kenta Ogawa
  • Patent number: RE45987
    Abstract: An external terminal of an electronic component is provided with a lead base material and a metal thin film coating a surface of the lead base material, and an average value of a crystal size index is not less than 7, which is defined based on dimensions of a crystal particle in a direction perpendicular to the lead base material surface and in a direction parallel thereto, taken on a cut surface of the metal thin film defined by a given plane cutting the metal thin film in a direction perpendicular to the lead base material surface. Such constitution provides an electronic component having an external terminal coated with a metal thin film of a simple structure constituted of Sn or a Sn-based and substantially Pb-free alloy, formed by plating on a surface of a lead base material.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: April 26, 2016
    Assignee: RENESAS ELECTRONICS COPORATION
    Inventor: Kenta Ogawa