Patents by Inventor Kenta Ogawa
Kenta Ogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8772914Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.Type: GrantFiled: January 15, 2013Date of Patent: July 8, 2014Assignee: Renesas Electronics CorporationInventors: Yasutaka Nakashiba, Kenta Ogawa
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Patent number: 8753922Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.Type: GrantFiled: January 15, 2013Date of Patent: June 17, 2014Assignee: Renesas Electronics CorporationInventors: Yasutaka Nakashiba, Kenta Ogawa
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Patent number: 8705238Abstract: A storage element is provided in a semiconductor chip, and an inductor and a driver circuit are provided in another semiconductor chip. An external terminal is a contact type terminal, and at least some external terminals are a power supply terminal and a ground terminal. A sealing resin layer is formed over a first surface of an interconnect substrate and seals the semiconductor chips but does not cover the external terminal. The inductor is formed at a surface of the semiconductor chip not facing the interconnect substrate.Type: GrantFiled: December 6, 2010Date of Patent: April 22, 2014Assignee: Renesas Electronics CorporationInventors: Yasutaka Nakashiba, Kenta Ogawa
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Patent number: 8389414Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.Type: GrantFiled: February 14, 2011Date of Patent: March 5, 2013Assignees: NEC Corporation, Renesas Electronics CorporationInventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
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Publication number: 20130043558Abstract: A semiconductor device, includes a substrate with a first surface, a semiconductor chip disposed over the first surface of the substrate, the semiconductor chip including a first region and a second region, and an encapsulant resin formed over the first surface of the substrate and encapsulating the semiconductor chip. The encapsulant resin has a thickness that is less at the first region of the semiconductor chip than that at the second region.Type: ApplicationFiled: September 15, 2012Publication date: February 21, 2013Applicant: Renesas Electronics CorporationInventors: Yasutaka NAKASHIBA, Kenta Ogawa
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Patent number: 8378470Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.Type: GrantFiled: September 2, 2010Date of Patent: February 19, 2013Assignee: Renesas Electronics CorporationInventors: Yasutaka Nakashiba, Kenta Ogawa
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Patent number: 8357935Abstract: In order to solve the above problem, provided is an electronic component having an authentication pattern formed on an exposed surface, in which the authentication pattern includes a base section including a resin and colored particles having a hue that can be identified in the base section, and the colored particles are dispersed so as to form dotted pattern in the base section.Type: GrantFiled: August 1, 2011Date of Patent: January 22, 2013Assignee: Renesas Electronics CorporationInventors: Yasuhiro Matsumaru, Kenta Ogawa
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Patent number: 8283770Abstract: A semiconductor module includes a semiconductor device including a mounting board, a semiconductor chip disposed at a first surface of the mounting board, a first inductor which is provided at a surface side of the semiconductor chip not facing the mounting board in order to perform communication between the semiconductor chip and the outside, a sealing resin layer which is formed at the first surface of the mounting board in order to seal the semiconductor chip, and a recess or an opening which is provided in the sealing resin layer and which includes the inductor inside when seen in a plan view; and a second inductor, which is located in the recess or the opening of the semiconductor device so that the second inductor performs communication with the first inductor.Type: GrantFiled: June 8, 2011Date of Patent: October 9, 2012Assignee: Renesas Electronics CorporationInventors: Yasutaka Nakashiba, Kenta Ogawa
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Publication number: 20120043648Abstract: In order to solve the above problem, provided is an electronic component having an authentication pattern formed on an exposed surface, in which the authentication pattern includes a base section including a resin and colored particles having a hue that can be identified in the base section, and the colored particles are dispersed so as to form dotted pattern in the base section.Type: ApplicationFiled: August 1, 2011Publication date: February 23, 2012Applicant: Renesas Electronics CorporationInventors: Yasuhiro MATSUMARU, Kenta OGAWA
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Publication number: 20120045114Abstract: There is provided an authentication device including an authentication information storage unit that stores authentication information acquired from an authentication pattern including a part or the entirety of a mottled pattern or a dot pattern formed over an electronic component as information for indentifying each of a plurality of electronic components, an authentication information acquiring unit that acquires a first authentication information acquired from the authentication pattern formed over a first electronic component that is an object to be authenticated, a search unit that searches whether or not the authentication information storage unit stores the first authentication information by using the first authentication information as a search key, and an output unit that outputs a search result of the search unit.Type: ApplicationFiled: August 3, 2011Publication date: February 23, 2012Applicant: Renesas Electronics CorporationInventors: Yasuhiro Matsumaru, Kenta Ogawa
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Publication number: 20110241165Abstract: A semiconductor module includes a semiconductor device including a mounting board, a semiconductor chip disposed at a first surface of the mounting board, a first inductor which is provided at a surface side of the semiconductor chip not facing the mounting board in order to perform communication between the semiconductor chip and the outside, a sealing resin layer which is formed at the first surface of the mounting board in order to seal the semiconductor chip, and a recess or an opening which is provided in the sealing resin layer and which includes the inductor inside when seen in a plan view; and a second inductor, which is located in the recess or the opening of the semiconductor device so that the second inductor performs communication with the first inductor.Type: ApplicationFiled: June 8, 2011Publication date: October 6, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yasutaka Nakashiba, Kenta Ogawa
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Publication number: 20110223998Abstract: To provide a game device capable of improving operability of operation means. First acquisition means (61) acquires information regarding an operation state of an operation member included in the operation means. Second acquisition means (62) acquires information regarding a change in position or posture of the operation means. First control means (63) causes an operation target to perform a first action based on a result acquired by the first acquisition means (61). Second control means (64) causes the operation target to perform a second action based on a result acquired by the second acquisition means (62).Type: ApplicationFiled: June 30, 2009Publication date: September 15, 2011Applicant: KONAMI DIGITAL ENTERTAINMENT CO., LTD.Inventors: Hiroshige Asano, Kazuma Tsurumoto, Koji Ishii, Yukihiro Hojo, Kenta Ogawa, Satoshi Koyama, Tadakatsu Izumi, Shota Osaka, Junichi Taya
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Patent number: 7982303Abstract: A semiconductor chip is disposed on a first surface of a mounting board with its active surface upward. An inductor is provided at the active surface side, that is, at the surface side of the semiconductor chip not facing the mounting board in order to perform communication between the semiconductor chip and the outside. A sealing resin layer is formed on the first surface of the mounting board in order to seal the semiconductor chip. In addition, a recess or an opening (in the present embodiment, a recess) is provided in the sealing resin layer. The recess includes the inductor thereinside when seen in a plan view.Type: GrantFiled: December 6, 2010Date of Patent: July 19, 2011Assignee: Renesas Electronics CorporationInventors: Yasutaka Nakashiba, Kenta Ogawa
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Publication number: 20110141681Abstract: A storage element is provided in a semiconductor chip, and an inductor and a driver circuit are provided in another semiconductor chip. An external terminal is a contact type terminal, and at least some external terminals are a power supply terminal and a ground terminal. A sealing resin layer is formed over a first surface of an interconnect substrate and seals the semiconductor chips but does not cover the external terminal. The inductor is formed at a surface of the semiconductor chip not facing the interconnect substrate.Type: ApplicationFiled: December 6, 2010Publication date: June 16, 2011Applicant: Renesas Electronics CorporationInventors: Yasutaka Nakashiba, Kenta Ogawa
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Publication number: 20110143662Abstract: A semiconductor chip is disposed on a first surface of a mounting board with its active surface upward. An inductor is provided at the active surface side, that is, at the surface side of the semiconductor chip not facing the mounting board in order to perform communication between the semiconductor chip and the outside. A sealing resin layer is formed on the first surface of the mounting board in order to seal the semiconductor chip. In addition, a recess or an opening (in the present embodiment, a recess) is provided in the sealing resin layer. The recess includes the inductor thereinside when seen in a plan view.Type: ApplicationFiled: December 6, 2010Publication date: June 16, 2011Applicant: Renesas Electronics CorporationInventors: Yasutaka Nakashiba, Kenta Ogawa
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Publication number: 20110136298Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.Type: ApplicationFiled: February 14, 2011Publication date: June 9, 2011Applicants: NEC CORPORATION, RENESAS ELECTRONICS CORPORATIONInventors: Katsumi KIKUCHI, Shintaro YAMAMICHI, Hideya MURAI, Takuo FUNAYA, Kentaro MORI, Takehiko MAEDA, Hirokazu HONDA, Kenta OGAWA, Jun TSUKANO
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Patent number: 7911038Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.Type: GrantFiled: June 29, 2007Date of Patent: March 22, 2011Assignee: Renesas Electronics CorporationInventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
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Publication number: 20110049693Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.Type: ApplicationFiled: September 2, 2010Publication date: March 3, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yasutaka NAKASHIBA, Kenta OGAWA
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Patent number: 7838779Abstract: A wiring board in which lower-layer wiring composed of a wiring body and an etching barrier layer is formed in a concave portion formed on one face of a board-insulating film, upper-layer wiring is formed on the other face of the board-insulating film, and the upper-layer wiring and the wiring body of the lower-layer wiring are connected to each other through a via hole formed in the board-insulating film. The via hole is barrel-shaped, bell-shaped, or bellows-shaped.Type: GrantFiled: June 15, 2006Date of Patent: November 23, 2010Assignees: NEC Corporation, NEC Electronics CorporationInventors: Shintaro Yamamichi, Katsumi Kikuchi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Kenta Ogawa, Jun Tsukano, Hirokazu Honda
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Publication number: 20100258955Abstract: The semiconductor device includes a substrate over one surface of which an electroless plating electrode film is formed; a semiconductor chip mounted over the one surface of the substrate; and a bonding wire which connects the semiconductor chip and one surface of the electroless plating electrode film, a recessed depth which is a difference between a lowermost height of a bonding portion of the one surface of the electroless plating electrode film to the bonding wire, and an uppermost height of the one surface other than the bonding portion being equal to or less than 1.5 ?m.Type: ApplicationFiled: April 9, 2010Publication date: October 14, 2010Applicant: NEC ELECTRONICS CORPORATIONInventors: YUICHI MIYAGAWA, HIDEYUKI HORII, KENTA OGAWA