Patents by Inventor Kentaro Matsunaga
Kentaro Matsunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9306221Abstract: A fuel electrode for a solid oxide electrochemical cell includes: an electrode layer constituted of a mixed phase including an oxide having mixed conductivity and another oxide selected from the group including an aluminum-based oxide and a magnesium-based composite oxide, said another oxide having, supported on a surface part thereof, particles of at least one member selected from nickel, cobalt, and nickel-cobalt alloys.Type: GrantFiled: March 14, 2013Date of Patent: April 5, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Fukasawa, Keizo Shimamura, Yoshio Hanakata, Masato Yoshino, Kentaro Matsunaga, Tsuneji Kameda, Yoshiyasu Itoh
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Publication number: 20160064216Abstract: According to an embodiment, a guide pattern having a first opening pattern and a second opening pattern shallower than the first opening pattern, is formed on a film to be processed. A directed self-assembly material is set into the first and second opening patterns. The directed self-assembly material is phase-separated into first and second phases in the first and second opening patterns. A third opening pattern is formed by removing the first phase. The third opening pattern in the second opening pattern is eliminated, and the second and third opening patterns are transferred to the film to be processed, by one etching to be processed from the tops of the second and third opening patterns.Type: ApplicationFiled: December 19, 2014Publication date: March 3, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Sonoe NAKAOKA, Kentaro Matsunaga, Eiji Yoneda
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Patent number: 9260300Abstract: According one embodiment, a pattern formation method forming a resist layer on a pattern formation surface by pressing a template provided with a concave-convex from above the resist layer to form a resist pattern on the pattern formation surface, includes: forming a resist layer in a first region having an area smaller than an area of the pattern formation surface and in a second region other than the first region of the pattern formation surface; pressing a template against the resist layer; irradiating the resist layer with light via the template to form a first resist layer in the first region, curing of the first resist layer being suppressed, and form the resist pattern including a second resist layer, curing of the second resist layer proceeds in the second region; and removing the first resist layer from the first region, the curing of the first resist layer being suppressed.Type: GrantFiled: July 30, 2013Date of Patent: February 16, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Kentaro Matsunaga, Nobuhiro Komine, Eiji Yoneda
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Publication number: 20160020099Abstract: According to one embodiment, first, an embedment material is embedded between linear core material patterns in such a manner that a height thereof becomes lower than a height of each of the core material patterns. Then, a shrink agent is supplied and solidified on the embedment material. Subsequently, the solidified shrink agent and the embedment material are removed and a spacer film is formed on an object of processing. Then, the spacer film is etched-back and a spacer pattern is formed by removal of the core material patterns. The solidified shrink agent which is formed in such a manner that a width of the spacer pattern becomes narrow in a region corresponding to a position where the shrink agent, in a sectional surface vertical to an extended direction of the spacer pattern is supplied is removed.Type: ApplicationFiled: December 17, 2014Publication date: January 21, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Kazuhiro SEGAWA, Nobuhiro KOMINE, Kentaro MATSUNAGA, Takehiro KONDOH, Shinichi NAKAGAWA
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Publication number: 20150357410Abstract: According to one embodiment, it includes an object film and an opening that is formed in the object film and in which a second taper adjoining a first taper is provided. A step is provided at the boundary between the first taper and the second taper.Type: ApplicationFiled: September 10, 2014Publication date: December 10, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Takuya MIZUTANI, Yuji SETTA, Kentaro MATSUNAGA
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Patent number: 9209052Abstract: A semiconductor manufacturing apparatus according to the present embodiment includes a vacuum chamber. A stage mounts a semiconductor substrate thereon within the vacuum chamber. An electrostatic chuck fixes the semiconductor substrate onto the stage. A sensor detects a height of a surface of the semiconductor substrate fixed onto the stage by the electrostatic chuck. A processor determines whether the surface of the semiconductor substrate is distorted based on the height of the surface of the semiconductor substrate. The processor calculates correction values for a pattern transferred onto the surface of the semiconductor substrate by exposure based on the height of the surface of the semiconductor substrate when the surface of the semiconductor substrate is distorted. An exposure part exposes the surface of the semiconductor substrate to light using the correction values.Type: GrantFiled: August 12, 2013Date of Patent: December 8, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yumi Nakajima, Kentaro Matsunaga, Eiji Yoneda
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Patent number: 9153456Abstract: According to one embodiment, first, on a process object, a hydrophilic guide pattern including a first hole forming pattern having a first hole diameter and a second hole forming pattern having a second hole diameter is formed. Then, above the guide pattern, a frame pattern having a first opening region in a forming region of a plurality of the first hole forming patterns and a second opening region in a forming region of a plurality of the second hole forming patterns is formed. Then, a first solution including a first block copolymer having a hydrophilic polymer chain and a hydrophobic polymer chain is supplied to the first opening region to condense the first block copolymer. The hydrophilic polymer chain is then removed to reduce the diameter of the first hole forming pattern to a third hole diameter that is smaller than the first hole diameter.Type: GrantFiled: December 9, 2013Date of Patent: October 6, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yumi Nakajima, Kentaro Matsunaga
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Patent number: 9070559Abstract: According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer. Next, the spacer film is etch-backed. Subsequently, an embedded layer is embedded between the core patterns whose peripheral areas are surrounded by the spacer film. Then, the core pattern and the embedded layer are removed simultaneously. Subsequently, using the spacer pattern as a mask, the hard mask layer and the process object are processed.Type: GrantFiled: March 4, 2014Date of Patent: June 30, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Seiro Miyoshi, Maki Miyazaki, Kentaro Matsunaga
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Publication number: 20150168841Abstract: According to one embodiment, first a guide pattern is formed above an object to processing, and then surface modification is performed on the guide pattern. Then a solution including a block copolymer is coated over the object to processing having the guide pattern formed thereon, and the block copolymer is made to phase separate over the object to processing. Subsequently, one component of the phase-separated block copolymer is removed by development. And with the guide pattern coated with other component of the block copolymer as a mask, the object to processing is patterned.Type: ApplicationFiled: February 28, 2014Publication date: June 18, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Kentaro MATSUNAGA, Masashi Terao, Eiji Yoneda
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Patent number: 9034766Abstract: According to one embodiment, a pattern formation method includes: forming a first guide layer having of first openings exposing a surface of an underlayer, and the first openings being arranged in a first direction; forming a second guide layer on the underlayer and on the first guide layer, the second guide layer extending in the first direction, the second guide layer dividing each of the first openings into the first opening portion and the second opening portion, and the second guide layer being sandwiched by a first opening portion and a second opening portion; forming a block copolymer layer in each of the first opening portion and the second opening portion; forming a first layer and a second layer surrounded by the first layer in each of the first opening portion and the second opening portion by phase-separating the block copolymer layer; and removing the second layer.Type: GrantFiled: February 12, 2014Date of Patent: May 19, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kentaro Matsunaga, Yoshihiro Yanai, Hirokazu Kato
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Patent number: 8999600Abstract: A solid oxide electrochemical cell of an embodiment includes: a cathode; an anode; and an electrolyte layer interposed between the cathode and the anode, wherein a porous region exists in a layer form in a region with a depth of 50% or less of the electrolyte layer from an anode side surface toward the cathode in the electrolyte layer or between the electrolyte layer and the anode.Type: GrantFiled: February 14, 2013Date of Patent: April 7, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Norikazu Osada, Takayuki Fukasawa, Tsuneji Kameda, Kentaro Matsunaga, Masato Yoshino
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Publication number: 20150044874Abstract: According to one embodiment, a pattern formation method includes: forming a first guide layer having of first openings exposing a surface of an underlayer, and the first openings being arranged in a first direction; forming a second guide layer on the underlayer and on the first guide layer, the second guide layer extending in the first direction, the second guide layer dividing each of the first openings into the first opening portion and the second opening portion, and the second guide layer being sandwiched by a first opening portion and a second opening portion; forming a block copolymer layer in each of the first opening portion and the second opening portion; forming a first layer and a second layer surrounded by the first layer in each of the first opening portion and the second opening portion by phase-separating the block copolymer layer; and removing the second layer.Type: ApplicationFiled: February 12, 2014Publication date: February 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Kentaro MATSUNAGA, Yoshihiro YANAI, Hirokazu KATO
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Publication number: 20150031198Abstract: According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer. Next, the spacer film is etch-backed. Subsequently, an embedded layer is embedded between the core patterns whose peripheral areas are surrounded by the spacer film. Then, the core pattern and the embedded layer are removed simultaneously. Subsequently, using the spacer pattern as a mask, the hard mask layer and the process object are processed.Type: ApplicationFiled: March 4, 2014Publication date: January 29, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Seiro MIYOSHI, Maki MIYAZAKI, Kentaro MATSUNAGA
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Publication number: 20140377956Abstract: According to one embodiment, first, on a process object, a hydrophilic guide pattern including a first hole forming pattern having a first hole diameter and a second hole forming pattern having a second hole diameter is formed. Then, above the guide pattern, a frame pattern having a first opening region in a forming region of a plurality of the first hole forming patterns and a second opening region in a forming region of a plurality of the second hole forming patterns is formed. Then, a first solution including a first block copolymer having a hydrophilic polymer chain and a hydrophobic polymer chain is supplied to the first opening region to condense the first block copolymer. The hydrophilic polymer chain is then removed to reduce the diameter of the first hole forming pattern to a third hole diameter that is smaller than the first hole diameter.Type: ApplicationFiled: December 9, 2013Publication date: December 25, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yumi NAKAJIMA, Kentaro Matsunaga
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Publication number: 20140227807Abstract: A semiconductor manufacturing apparatus according to the present embodiment includes a vacuum chamber. A stage mounts a semiconductor substrate thereon within the vacuum chamber. An electrostatic chuck fixes the semiconductor substrate onto the stage. A sensor detects a height of a surface of the semiconductor substrate fixed onto the stage by the electrostatic chuck. A processor determines whether the surface of the semiconductor substrate is distorted based on the height of the surface of the semiconductor substrate. The processor calculates correction values for a pattern transferred onto the surface of the semiconductor substrate by exposure based on the height of the surface of the semiconductor substrate when the surface of the semiconductor substrate is distorted. An exposure part exposes the surface of the semiconductor substrate to light using the correction values.Type: ApplicationFiled: August 12, 2013Publication date: August 14, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yumi NAKAJIMA, Kentaro MATSUNAGA, Eiji YONEDA
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Publication number: 20140213058Abstract: According one embodiment, a pattern formation method forming a resist layer on a pattern formation surface by pressing a template provided with a concave-convex from above the resist layer to form a resist pattern on the pattern formation surface, includes: forming a resist layer in a first region having an area smaller than an area of the pattern formation surface and in a second region other than the first region of the pattern formation surface; pressing a template against the resist layer; irradiating the resist layer with light via the template to form a first resist layer in the first region, curing of the first resist layer being suppressed, and form the resist pattern including a second resist layer, curing of the second resist layer proceeds in the second region; and removing the first resist layer from the first region, the curing of the first resist layer being suppressed.Type: ApplicationFiled: July 30, 2013Publication date: July 31, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kentaro Matsunaga, Nobuhiro Komine, Eiji Yoneda
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Patent number: 8747682Abstract: According to one embodiment, a pattern formation method is disclosed. The method includes forming a plurality of regions on a foundation and the plurality of the regions correspond to different pattern sizes. The method includes separating each of a plurality of block copolymers from another one of the plurality of the block copolymers and segregating the each of the plurality of the block copolymers into a corresponding one of the regions. The method includes performing a phase separation of the each of the block copolymers of each of the regions. The method includes selectively removing a designated phase of each of the phase-separated block copolymers to form a pattern of the each of the block copolymers and the pattern has a different pattern size for the each of the regions.Type: GrantFiled: August 3, 2010Date of Patent: June 10, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kentaro Matsunaga, Tomoya Oori, Eishi Shiobara, Yukiko Sato, Yoshihisa Kawamura
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Publication number: 20140063477Abstract: According to one embodiment, an EUV exposure apparatus includes a mirror which reflects an EUV light beam irradiated from a light source and a wafer stage which is irradiated with the EUV light beam reflected by the mirror. When exposure of a first wafer is to be performed, the first wafer is mounted on the wafer stage, and the wafer stage allows the first wafer to be irradiated with the EUV light beam. In addition, when cleaning of the mirror is to be performed, the EUV light beam is reflected by a reflection substrate, and the wafer stage allows the mirror to be irradiated with the reflected light beam.Type: ApplicationFiled: February 20, 2013Publication date: March 6, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kentaro MATSUNAGA
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Publication number: 20130248360Abstract: A solid oxide electrochemical cell of an embodiment includes: a cathode; an anode; and an electrolyte layer interposed between the cathode and the anode, wherein a porous region exists in a layer form in a region with a depth of 50% or less of the electrolyte layer from an anode side surface toward the cathode in the electrolyte layer or between the electrolyte layer and the anode.Type: ApplicationFiled: February 14, 2013Publication date: September 26, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Norikazu Osada, Takayuki Fukasawa, Tsuneji Kameda, Kentaro Matsunaga, Masato Yoshino
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Patent number: 8419995Abstract: An imprint method includes applying a light curable resin on a substrate to be processed, the substrate including first and second regions on which the light curable resin is applied, contacting an imprint mold with the light curable resin, curing the light curable resin by irradiating the light curable resin with light passing through the imprint mold, generating gas by performing a predetermined process to the light curable resin applied on a region of the substrate, the region including at least the first region, wherein an amount of gas generated from the light curable resin applied on the first region is larger than an amount of gas generated from the light curable resin of the second region, and forming a pattern by separating the imprint mold from the light curable resin after the gas being generated.Type: GrantFiled: September 21, 2009Date of Patent: April 16, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Ikuo Yoneda, Kentaro Matsunaga, Yukiko Kikuchi, Yoshihisa Kawamura, Eishi Shiobara, Shinichi Ito, Tetsuro Nakasugi, Hirokazu Kato