Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.

Abstract: A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.

Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.

Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.

Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.

Abstract: A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.

Abstract: The semiconductor device may include a first sub-pipe gate having a pipe hole formed therein; a second sub-pipe gate disposed on the first sub-pipe gate and passed-through by vertical holes being coupled to the pipe hole, wherein a material of the second sub-pipe gate has a lower oxidation rate than that of a material of the first sub-pipe gate; a first oxidized layer formed within a portion of the first sub-pipe gate to conform to a contour of the pipe hole; and a second oxidized layer formed within a portion of the second sub-pipe gate to conform to a contour of the vertical holes and the contour of the pipe hole.

Abstract: The semiconductor device may include a first sub-pipe gate having a pipe hole formed therein; a second sub-pipe gate disposed on the first sub-pipe gate and passed-through by vertical holes being coupled to the pipe hole, wherein a material of the second sub-pipe gate has a lower oxidation rate than that of a material of the first sub-pipe gate; a first oxidized layer formed within a portion of the first sub-pipe gate to conform to a contour of the pipe hole; and a second oxidized layer formed within a portion of the second sub-pipe gate to conform to a contour of the vertical holes and the contour of the pipe hole.

Abstract: A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.

Abstract: A semiconductor device includes a memory array including memory blocks, and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the operation circuit performs the program loop on the selection transistors so that a difference occurs between threshold voltages of the selection transistors and a target threshold voltage based on a difference between a cell current value of the selected memory block and a reference cell current value.

Abstract: A semiconductor device according to an embodiment may include a memory string including a drain selection transistor, memory cells and a source selection transistor all coupled between a bit line and a common source line, and the drain selection transistor, the memory cells and the source selection transistor configured to operate, respectively, in response to voltages applied to a drain selection line, word lines and a source selection line. The semiconductor device may include an operation circuit configured for performing a program operation. The operation circuit may be configured for sequentially performing a first operation, a second operation, and a third operation. In the first operation memory cells adjacent to the drain selection transistor may be programmed. In the second operation memory cells adjacent to the source selection transistor may be programmed. In the third operation remaining memory cells may be programmed.

Abstract: A semiconductor memory device and a method of operating the same are provided. The device may include a memory cell array including a plurality of memory blocks and a peripheral circuit configured for selecting one of the plurality of memory blocks and performing a program operation on selected memory cells of the selected memory block when the program operation is performed. The peripheral circuit may be configured to float a plurality of source select lines and a plurality of drain select lines of an unselected memory block of the plurality of memory blocks when the program operation is performed.

Abstract: Disclosed are a semiconductor memory device, a memory system including the same, and an operating method thereof. The memory system includes: a semiconductor memory device including a plurality of memory chips; and a controller configured to measure a cell current of each of the plurality of memory chips, generate temperature compensation data corresponding to the measured cell current, and store the generated temperature compensation data in each of the plurality of memory chips.

Abstract: A semiconductor device may include memory blocks having a plurality of strings including drain select transistors and memory cells electrically coupled in series between a bit line and a pipe transistor and source select transistors and memory cells electrically coupled in series between a common source line and the pipe transistor; a circuit group configured to float drain select lines electrically coupled to the drain select transistors included in unselected memory blocks and source select lines electrically coupled to the source select transistors included in the unselected memory blocks and to ground a pipe line electrically coupled to the pipe transistor when a program operation of a selected memory block among the memory blocks is performed; and a control circuit configured to control the circuit group.

Abstract: A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.

Abstract: A semiconductor memory device and a method of operating the same are provided. The device may include a memory cell array including a plurality of memory blocks and a peripheral circuit configured for selecting one of the plurality of memory blocks and performing a program operation on selected memory cells of the selected memory block when the program operation is performed. The peripheral circuit may be configured to float a plurality of source select lines and a plurality of drain select lines of an unselected memory block of the plurality of memory blocks when the program operation is performed.

Abstract: A semiconductor device includes a memory array including memory blocks, and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the operation circuit performs the program loop on the selection transistors so that a difference occurs between threshold voltages of the selection transistors and a target threshold voltage based on a difference between a cell current value of the selected memory block and a reference cell current value.

Abstract: A semiconductor device according to an embodiment may include a memory string including a drain selection transistor, memory cells and a source selection transistor all coupled between a bit line and a common source line, and the drain selection transistor, the memory cells and the source selection transistor configured to operate, respectively, in response to voltages applied to a drain selection line, word lines and a source selection line. The semiconductor device may include an operation circuit configured for performing a program operation. The operation circuit may be configured for sequentially performing a first operation, a second operation, and a third operation. In the first operation memory cells adjacent to the drain selection transistor may be programmed. In the second operation memory cells adjacent to the source selection transistor may be programmed. In the third operation remaining memory cells may be programmed.

Abstract: A semiconductor device may include memory blocks having a plurality of strings including drain select transistors and memory cells electrically coupled in series between a bit line and a pipe transistor and source select transistors and memory cells electrically coupled in series between a common source line and the pipe transistor; a circuit group configured to float drain select lines electrically coupled to the drain select transistors included in unselected memory blocks and source select lines electrically coupled to the source select transistors included in the unselected memory blocks and to ground a pipe line electrically coupled to the pipe transistor when a program operation of a selected memory block among the memory blocks is performed; and a control circuit configured to control the circuit group.

Abstract: A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.