Patents by Inventor Keon Soo Shim

Keon Soo Shim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210165603
    Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.
    Type: Application
    Filed: February 11, 2021
    Publication date: June 3, 2021
    Applicant: SK hynix Inc.
    Inventors: Byung In LEE, Hee Joung PARK, Keon Soo SHIM, Sang Heon LEE, Jae Il TAK
  • Patent number: 10950306
    Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Byung In Lee, Hee Joung Park, Keon Soo Shim, Sang Heon Lee, Jae Il Tak
  • Publication number: 20200211650
    Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.
    Type: Application
    Filed: July 12, 2019
    Publication date: July 2, 2020
    Applicant: SK hynix Inc.
    Inventors: Byung In LEE, Hee Joung PARK, Keon Soo SHIM, Sang Heon LEE, Jae Il TAK
  • Patent number: 9853041
    Abstract: A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: December 26, 2017
    Assignee: SK Hynix Inc.
    Inventor: Keon Soo Shim
  • Patent number: 9711517
    Abstract: The semiconductor device may include a first sub-pipe gate having a pipe hole formed therein; a second sub-pipe gate disposed on the first sub-pipe gate and passed-through by vertical holes being coupled to the pipe hole, wherein a material of the second sub-pipe gate has a lower oxidation rate than that of a material of the first sub-pipe gate; a first oxidized layer formed within a portion of the first sub-pipe gate to conform to a contour of the pipe hole; and a second oxidized layer formed within a portion of the second sub-pipe gate to conform to a contour of the vertical holes and the contour of the pipe hole.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: July 18, 2017
    Assignee: SK Hynix Inc.
    Inventors: Keon Soo Shim, Seul Ki Oh, Eun Seok Choi
  • Publication number: 20170110468
    Abstract: The semiconductor device may include a first sub-pipe gate having a pipe hole formed therein; a second sub-pipe gate disposed on the first sub-pipe gate and passed-through by vertical holes being coupled to the pipe hole, wherein a material of the second sub-pipe gate has a lower oxidation rate than that of a material of the first sub-pipe gate; a first oxidized layer formed within a portion of the first sub-pipe gate to conform to a contour of the pipe hole; and a second oxidized layer formed within a portion of the second sub-pipe gate to conform to a contour of the vertical holes and the contour of the pipe hole.
    Type: Application
    Filed: March 22, 2016
    Publication date: April 20, 2017
    Inventors: Keon Soo SHIM, Seul Ki OH, Eun Seok CHOI
  • Patent number: 9627078
    Abstract: A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: April 18, 2017
    Assignee: SK Hynix Inc.
    Inventors: Yoo Nam Jeon, Keon Soo Shim, Hae Soon Oh, Bong Yeol Park
  • Patent number: 9620224
    Abstract: A semiconductor device includes a memory array including memory blocks, and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the operation circuit performs the program loop on the selection transistors so that a difference occurs between threshold voltages of the selection transistors and a target threshold voltage based on a difference between a cell current value of the selected memory block and a reference cell current value.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: April 11, 2017
    Assignee: SK Hynix Inc.
    Inventors: Yoo Nam Jeon, Keon Soo Shim, Hae Soon Oh, Bong Yeol Park
  • Patent number: 9424935
    Abstract: A semiconductor device according to an embodiment may include a memory string including a drain selection transistor, memory cells and a source selection transistor all coupled between a bit line and a common source line, and the drain selection transistor, the memory cells and the source selection transistor configured to operate, respectively, in response to voltages applied to a drain selection line, word lines and a source selection line. The semiconductor device may include an operation circuit configured for performing a program operation. The operation circuit may be configured for sequentially performing a first operation, a second operation, and a third operation. In the first operation memory cells adjacent to the drain selection transistor may be programmed. In the second operation memory cells adjacent to the source selection transistor may be programmed. In the third operation remaining memory cells may be programmed.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: August 23, 2016
    Assignee: SK HYNIX INC.
    Inventor: Keon Soo Shim
  • Patent number: 9396799
    Abstract: A semiconductor memory device and a method of operating the same are provided. The device may include a memory cell array including a plurality of memory blocks and a peripheral circuit configured for selecting one of the plurality of memory blocks and performing a program operation on selected memory cells of the selected memory block when the program operation is performed. The peripheral circuit may be configured to float a plurality of source select lines and a plurality of drain select lines of an unselected memory block of the plurality of memory blocks when the program operation is performed.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: July 19, 2016
    Assignee: Sk hynix Inc.
    Inventor: Keon Soo Shim
  • Patent number: 9384841
    Abstract: A semiconductor device may include memory blocks having a plurality of strings including drain select transistors and memory cells electrically coupled in series between a bit line and a pipe transistor and source select transistors and memory cells electrically coupled in series between a common source line and the pipe transistor; a circuit group configured to float drain select lines electrically coupled to the drain select transistors included in unselected memory blocks and source select lines electrically coupled to the source select transistors included in the unselected memory blocks and to ground a pipe line electrically coupled to the pipe transistor when a program operation of a selected memory block among the memory blocks is performed; and a control circuit configured to control the circuit group.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: July 5, 2016
    Assignee: SK hynix Inc.
    Inventors: Keon Soo Shim, Hyun Seung Yoo
  • Patent number: 9384846
    Abstract: Disclosed are a semiconductor memory device, a memory system including the same, and an operating method thereof. The memory system includes: a semiconductor memory device including a plurality of memory chips; and a controller configured to measure a cell current of each of the plurality of memory chips, generate temperature compensation data corresponding to the measured cell current, and store the generated temperature compensation data in each of the plurality of memory chips.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: July 5, 2016
    Assignee: SK hynix Inc.
    Inventors: Keon Soo Shim, Bong Yeol Park
  • Publication number: 20160172047
    Abstract: A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.
    Type: Application
    Filed: February 9, 2016
    Publication date: June 16, 2016
    Inventors: Yoo Nam JEON, Keon Soo SHIM, Hae Soon OH, Bong Yeol PARK
  • Publication number: 20160141035
    Abstract: A semiconductor memory device and a method of operating the same are provided. The device may include a memory cell array including a plurality of memory blocks and a peripheral circuit configured for selecting one of the plurality of memory blocks and performing a program operation on selected memory cells of the selected memory block when the program operation is performed. The peripheral circuit may be configured to float a plurality of source select lines and a plurality of drain select lines of an unselected memory block of the plurality of memory blocks when the program operation is performed.
    Type: Application
    Filed: April 21, 2015
    Publication date: May 19, 2016
    Inventor: Keon Soo SHIM
  • Publication number: 20160125944
    Abstract: A semiconductor device according to an embodiment may include a memory string including a drain selection transistor, memory cells and a source selection transistor all coupled between a bit line and a common source line, and the drain selection transistor, the memory cells and the source selection transistor configured to operate, respectively, in response to voltages applied to a drain selection line, word lines and a source selection line. The semiconductor device may include an operation circuit configured for performing a program operation. The operation circuit may be configured for sequentially performing a first operation, a second operation, and a third operation. In the first operation memory cells adjacent to the drain selection transistor may be programmed. In the second operation memory cells adjacent to the source selection transistor may be programmed. In the third operation remaining memory cells may be programmed.
    Type: Application
    Filed: March 20, 2015
    Publication date: May 5, 2016
    Inventor: Keon Soo SHIM
  • Publication number: 20160125946
    Abstract: A semiconductor device includes a memory array including memory blocks, and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the operation circuit performs the program loop on the selection transistors so that a difference occurs between threshold voltages of the selection transistors and a target threshold voltage based on a difference between a cell current value of the selected memory block and a reference cell current value.
    Type: Application
    Filed: March 17, 2015
    Publication date: May 5, 2016
    Inventors: Yoo Nam JEON, Keon Soo SHIM, Hae Soon OH, Bong Yeol PARK
  • Publication number: 20150340096
    Abstract: A semiconductor device may include memory blocks having a plurality of strings including drain select transistors and memory cells electrically coupled in series between a bit line and a pipe transistor and source select transistors and memory cells electrically coupled in series between a common source line and the pipe transistor; a circuit group configured to float drain select lines electrically coupled to the drain select transistors included in unselected memory blocks and source select lines electrically coupled to the source select transistors included in the unselected memory blocks and to ground a pipe line electrically coupled to the pipe transistor when a program operation of a selected memory block among the memory blocks is performed; and a control circuit configured to control the circuit group.
    Type: Application
    Filed: September 26, 2014
    Publication date: November 26, 2015
    Inventors: Keon Soo SHIM, Hyun Seung YOO
  • Publication number: 20150236036
    Abstract: A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.
    Type: Application
    Filed: April 30, 2015
    Publication date: August 20, 2015
    Inventor: Keon Soo SHIM
  • Patent number: 9053796
    Abstract: A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: June 9, 2015
    Assignee: SK Hynix Inc.
    Inventor: Keon Soo Shim
  • Publication number: 20150117108
    Abstract: A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.
    Type: Application
    Filed: March 5, 2014
    Publication date: April 30, 2015
    Applicant: SK hynix Inc.
    Inventor: Keon Soo SHIM