Patents by Inventor Keon Soo Shim
Keon Soo Shim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9053796Abstract: A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.Type: GrantFiled: March 5, 2014Date of Patent: June 9, 2015Assignee: SK Hynix Inc.Inventor: Keon Soo Shim
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Publication number: 20150117108Abstract: A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.Type: ApplicationFiled: March 5, 2014Publication date: April 30, 2015Applicant: SK hynix Inc.Inventor: Keon Soo SHIM
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Patent number: 8929149Abstract: The semiconductor memory device includes a memory cell block including a plurality of memory cells, a peripheral circuit section configured to perform an erase loop including a supply operation supplying an erase voltage and an erase verification operation to erase data stored in the memory cells, a fail bit counter configured to count the number of memory cells not erased in an erase operation among the memory cells to generate a count signal based on a fail count corresponding to a counting result in the erase verification operation, and a controller configured to control the peripheral circuit section to set a new erase voltage by increasing an erase voltage, used in a previous erase loop, by a first step voltage or decreasing the erase voltage by a second step voltage based on the fail count, and perform the erase loop using the new erase voltage.Type: GrantFiled: August 31, 2012Date of Patent: January 6, 2015Assignee: SK Hynix Inc.Inventor: Keon Soo Shim
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Publication number: 20140043914Abstract: The semiconductor memory device includes a memory cell block including a plurality of memory cells, a peripheral circuit section configured to perform an erase loop including a supply operation supplying an erase voltage and an erase verification operation to erase data stored in the memory cells, a fail bit counter configured to count the number of memory cells not erased in an erase operation among the memory cells to generate a count signal based on a fail count corresponding to a counting result in the erase verification operation, and a controller configured to control the peripheral circuit section to set a new erase voltage by increasing an erase voltage, used in a previous erase loop, by a first step voltage or decreasing the erase voltage by a second step voltage based on the fail count, and perform the erase loop using the new erase voltage.Type: ApplicationFiled: August 31, 2012Publication date: February 13, 2014Inventor: Keon Soo SHIM
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Patent number: 8625359Abstract: A memory device comprises a drain select line, a source select line, word lines, and a string connected between a bit line and a common source line. A program-inhibited voltage is applied to the bit line and a first voltage of a positive potential is applied to the drain select line. A second voltage for activating a programmed memory cell is applied to a word line to which the programmed memory cell is connected. A programming operation is performed by applying a program voltage to a selected word line and applying a pass voltage to the unselected word lines.Type: GrantFiled: January 18, 2008Date of Patent: January 7, 2014Assignee: SK hynix Inc.Inventors: Yoo Nam Jeon, Keon Soo Shim
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Patent number: 8279675Abstract: A nonvolatile memory device including a bit line voltage supply unit configured to supply a power source voltage, a second voltage in which a second reference voltage has been subtracted from a third reference voltage, or a third voltage in which a first reference voltage has been subtracted from the third reference voltage according to data stored in a first latch unit, a second latch unit, and a third latch unit included in a page buffer, and a bit line voltage setting unit configured to transfer a voltage of 0 V or an output voltage of the bit line voltage supply unit to a bit line according to the data stored in the first, second, and third latch units.Type: GrantFiled: November 19, 2009Date of Patent: October 2, 2012Assignee: Hynix Semiconductor Inc.Inventors: Ju Yeab Lee, Keon Soo Shim
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Patent number: 7889557Abstract: A memory device capable of enlarging an interval between a source selection transistor and a memory cell adjacent to the source selection transistor, enlarging an interval between a drain selection transistor and a memory cell adjacent to the drain selection transistor, or enlarging the intervals between the source selection transistor and the memory cell adjacent to the source selection transistor and between the drain selection transistor and the memory cell adjacent to the drain selection transistor, prevents the memory cell adjacent to the source or drain selection transistor from being degraded in programming speed due to program disturbance.Type: GrantFiled: December 21, 2005Date of Patent: February 15, 2011Assignee: Hynix Semiconductor Inc.Inventors: Hee Sik Park, Keon Soo Shim, Jong Soon Leem
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Publication number: 20100246263Abstract: This patent relates to a non-volatile memory device and a driving method thereof. The non-volatile memory device includes a source select line in which a floating gate and a control gate are electrically connected to each other, a drain select line in which a floating gate and a control gate are electrically isolated from each other, and a plurality of word lines formed between the source select line and the drain select line.Type: ApplicationFiled: June 8, 2010Publication date: September 30, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Yoo Nam Jeon, Yong Mook Baek, Keon Soo Shim
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Publication number: 20100202197Abstract: An operation method includes performing a first program operation and a first program verification operation on an even page memory cell group wherein the first program operation is performed such that the even page memory cell group is programmed to have a threshold voltage less than a target threshold voltage, performing a second program operation and a second program verification operation on an odd page memory cell group neighboring the even page memory cell group when the first verification operation is passed, performing a third program operation and a third program verification operation on the even page memory cell group when the second verification operation is passed, wherein the third program operation is performed such that the even page memory cell group is programmed to have a threshold voltage which is equal to or higher than the target threshold voltage.Type: ApplicationFiled: December 31, 2009Publication date: August 12, 2010Inventor: Keon Soo SHIM
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Patent number: 7773429Abstract: This patent relates to a non-volatile memory device and a driving method thereof The non-volatile memory device includes a source select line in which a floating gate and a control gate are electrically connected to each other, a drain select line in which a floating gate and a control gate are electrically isolated from each other, and a plurality of word lines formed between the source select line and the drain select line.Type: GrantFiled: February 21, 2008Date of Patent: August 10, 2010Assignee: Hynix Semiconductor Inc.Inventors: Yoo Nam Jeon, Yong Mook Baek, Keon Soo Shim
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Publication number: 20100124124Abstract: A nonvolatile memory device including a bit line voltage supply unit configured to supply a power source voltage, a second voltage in which a second reference voltage has been subtracted from a third reference voltage, or a third voltage in which a first reference voltage has been subtracted from the third reference voltage according to data stored in a first latch unit, a second latch unit, and a third latch unit included in a page buffer, and a bit line voltage setting unit configured to transfer a voltage of 0 V or an output voltage of the bit line voltage supply unit to a bit line according to the data stored in the first, second, and third latch units.Type: ApplicationFiled: November 19, 2009Publication date: May 20, 2010Inventors: Ju Yeab Lee, Keon Soo Shim
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Patent number: 7567459Abstract: In a method of measuring a channel boosting voltage, a threshold voltage of a pass disturbance is measured in accordance with change of a pass voltage applied to a selected cell under the condition that the pass voltage having a certain level is provided to a cell not selected of erased cells. Subsequently, a threshold voltage of a program disturbance is measured in accordance with change of the pass voltage applied to the cell not selected under the condition that a program voltage having a certain level is provided to a cell selected of the erased cells. Then, the channel boosting voltage is measured by using a pass bias voltage applied when the threshold voltage of the pass disturbance is identical to that of the program disturbance. As a result, the channel boosting voltage is accurately monitored when a program operation is performed. Accordingly, a program disturbance characteristic may be easily detected, and also yield and fail may be easily analyzed.Type: GrantFiled: April 5, 2007Date of Patent: July 28, 2009Assignee: Hynix Semiconductor Inc.Inventor: Keon Soo Shim
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Patent number: 7518931Abstract: A method monitors an erase threshold voltage distribution in a NAND flash memory device. The method programs a main cell by applying a first program voltage to the main cell, and then measures a threshold voltage of the main cell. The method programs a peripheral cell using a second program voltage and a third program voltage, and then measures a threshold voltage of the peripheral cell. The method measures a threshold voltage of the main cell changed by the measured threshold voltage of the peripheral cell, and then may predict an initial erase threshold voltage distribution of a page of the peripheral cell by using an interference correlation between the measured threshold voltages of the main cell and the peripheral cell.Type: GrantFiled: September 5, 2007Date of Patent: April 14, 2009Assignee: Hynix Semiconductor Inc.Inventor: Keon Soo Shim
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Publication number: 20090067242Abstract: A memory device comprises a drain select line, a source select line, word lines, and a string connected between a bit line and a common source line. A program-inhibited voltage is applied to the bit line and a first voltage of a positive potential is applied to the drain select line. A second voltage for activating a programmed memory cell is applied to a word line to which the programmed memory cell is connected. A programming operation is performed by applying a program voltage to a selected word line and applying a pass voltage to the unselected word lines.Type: ApplicationFiled: January 18, 2008Publication date: March 12, 2009Applicant: Hynix Semiconductor Inc.Inventors: Yoo Nam Jeon, Keon Soo Shim
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Publication number: 20080205162Abstract: This patent relates to a non-volatile memory device and a driving method thereof The non-volatile memory device includes a source select line in which a floating gate and a control gate are electrically connected to each other, a drain select line in which a floating gate and a control gate are electrically isolated from each other, and a plurality of word lines formed between the source select line and the drain select line.Type: ApplicationFiled: February 21, 2008Publication date: August 28, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Yoo Nam Jeon, Yong Mook Baek, Keon Soo Shim
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Publication number: 20080055979Abstract: A method monitors an erase threshold voltage distribution in a NAND flash memory device. The method programs a main cell by applying a first program voltage to the main cell, and then measures a threshold voltage of the main cell. The method programs a peripheral cell using a second program voltage and a third program voltage, and then measures a threshold voltage of the peripheral cell. The method measures a threshold voltage of the main cell changed by the measured threshold voltage of the peripheral cell, and then may predict an initial erase threshold voltage distribution of a page of the peripheral cell by using an interference correlation between the measured threshold voltages of the main cell and the peripheral cell.Type: ApplicationFiled: September 5, 2007Publication date: March 6, 2008Applicant: Hynix Semiconductor Inc.Inventor: Keon Soo Shim
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Publication number: 20070247911Abstract: In a method of measuring a channel boosting voltage, a threshold voltage of a pass disturbance is measured in accordance with change of a pass voltage applied to a selected cell under the condition that the pass voltage having a certain level is provided to a cell not selected of erased cells. Subsequently, a threshold voltage of a program disturbance is measured in accordance with change of the pass voltage applied to the cell not selected under the condition that a program voltage having a certain level is provided to a cell selected of the erased cells. Then, the channel boosting voltage is measured by using a pass bias voltage applied when the threshold voltage of the pass disturbance is identical to that of the program disturbance. As a result, the channel boosting voltage is accurately monitored when a program operation is performed. Accordingly, a program disturbance characteristic may be easily detected, and also yield and fail may be easily analyzed.Type: ApplicationFiled: April 5, 2007Publication date: October 25, 2007Applicant: Hynix Semiconductor Inc.Inventor: Keon Soo Shim
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Patent number: 7268040Abstract: Disclosed herein is a method of manufacturing a flash memory device.Type: GrantFiled: April 8, 2005Date of Patent: September 11, 2007Assignee: Hynix Semiconductor Inc.Inventor: Keon Soo Shim
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Publication number: 20040196601Abstract: The disclosed is an electrostatic discharge protecting circuit using a flash cell, comprising: a plurality of flash cells connected between an I/O pad and a VSS line, a gate of each flash cell being connected to the I/O pad; and a resistor connected between a floating gate of each flash cell and the VSS line.Type: ApplicationFiled: December 17, 2003Publication date: October 7, 2004Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Keon Soo Shim
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Patent number: 6743676Abstract: The present invention relates to a method of forming a floating gate in a flash memory device. Upon formation of a device isolation film, a space of a lower polysilicon layer for a floating gate is defined, a bird's beak is formed on an internal surface of a trench by subsequent well sacrificial oxidization process and well oxidization process and an upper polysilicon layer for a floating gate is then formed, so that the space of the floating gate is formed. Therefore, the present invention can reduce the cost since a mask process is not required compared to an existing stepper method and the process cost since a planarization process using chemical mechanical polishing process (CMP) is not required compared to the self-aligned floating mode.Type: GrantFiled: November 4, 2002Date of Patent: June 1, 2004Assignee: Hynix Semiconductor Inc.Inventors: Sung Kee Park, Ki Seog Kim, Keun Woo Lee, Keon Soo Shim