Abstract: The invention discloses an integrated circuit that includes a first device in a first power domain; a second device in a second power domain; and an electrostatic discharge (ESD) bus coupled to the first and second devices for providing a current path to dissipate an ESD current during an ESD event occurring at the first or second device. The ESD bus is disposed across the first and second power domains without having a diode module interposed therebetween, thereby preventing the ESD current from flowing through the first and second devices.

Abstract: A microchip includes at least one I/O area surrounding at least one core circuit area. The I/O area further includes a first I/O cell having at least one first post-driver device connected to a first I/O pad; a second I/O cell having at least one second post-driver device connected to a second I/O pad; and an electrostatic discharge (ESD) cluster shared by the first I/O cell and the second I/O cell for protecting the same against ESD current during an ESD event, thereby reducing a total width of the first I/O cell and the second I/O cell.

Abstract: The present invention discloses an IC implemented with ESD protection system. In one embodiment, the includes a first device in a first power domain, and a second device in a second power domain. A buffer module is coupled between the first device and the second device for allowing a signal to pass across between the first and second devices during a normal operation, and for increasing an impedance between the first and second devices during an electrostatic discharge (ESD) event, thereby reducing a possibility of having an ESD current flow from the first device to the second device.

Abstract: One embodiment is a method of designing an integrated circuit (“IC”) using an online design platform system comprising a design platform provider, at least one electronic design automation (“EDA”) tool and at least one intellectual property (“IP”) library. The method comprises accessing the design platform provider using a computer remote from the design platform provider, wherein the remote computer is connected to the design platform provider and the accessing occurs via an Internet connection; providing access via the remote computer to the at least one EDA tool and the at least one IP library for enabling a user at the remote computer to design an IC; and providing at least one file comprising a final design of the IC directly from the online design platform system to a designated foundry.

Abstract: This invention discloses a ballasting resistor for an electrostatic discharge (ESD) device that comprises at least one first active region forming a source/drain of an ESD discharge transistor, at least one resistive element with a serpentine shape formed in a single layer of a semiconductor structure, wherein the resistive element has a first terminal coupled to the first active region and a second terminal coupled to a bonding pad including power supply (Vdd or Vss) pads.

Abstract: An I/O output circuit is disclosed for interfacing a first system operating at a first voltage with a second system operating at a second voltage higher than the first voltage. The I/O output circuit includes an output stage module having one or more PMOS transistors and one or more NMOS transistors for coupling with the second system. A switch module is coupled to the output stage module for selectively providing the PMOS and NMOS transistors with various gate biases. A feedback circuit is coupled between an I/O pad that couples the output stage module to the second system and the switch module for controlling the switch module to generate the gate biases in response to a voltage at the I/O pad, thereby ensuring voltages across gates of the PMOS and NMOS transistors to be within a predetermined range.

Abstract: In one embodiment, the disclosure relates to a method and apparatus for inter-chip wireless communication system. The system includes a first microprocessor having a plurality of non-contact ports and a first RF communication circuit integrated with the first microprocessor; a second microprocessor also having a plurality of non-contact ports and a second RF communication circuit integrated therein. An RF communication protocol can be configured to receive data from each of the non-contact ports in parallel, multiplex and translate the data to a serial RF signal. Data communication can be accomplished using the wireless communication circuit on each chip. The RF communication between the first and the second integrated circuits using the communication protocol defines a non capacitive-coupling of the first and the second die.

Abstract: A power-on control circuit includes a coupling device coupled to a first voltage supply. A first inverter, coupled between the coupling device and a complementary voltage, has an input node coupled to a second voltage supply with a supply voltage level lower than that of the first voltage supply. A level shifter, coupled between the first voltage supply and the complementary voltage, has a first input node connected to an output node of the first inverter and a second input node coupled to the second voltage supply, for generating the power-on control signal when the first voltage supply is powered up and the second voltage supply is turned off and for disabling the power-on control signal when the second voltage supply is subsequently powered up. The coupling device eliminates a leakage current path from the first voltage supply to the complementary voltage through the first inverter.

Abstract: An I/O output circuit is disclosed for interfacing a first system operating at a first voltage with a second system operating at a second voltage higher than the first voltage. The I/O output circuit includes an output stage module having one or more PMOS transistors and one or more NMOS transistors for coupling with the second system. A switch module is coupled to the output stage module for selectively providing the PMOS and NMOS transistors with various gate biases. A feedback circuit is coupled between an I/O pad that couples the output stage module to the second system and the switch module for controlling the switch module to generate the gate biases in response to a voltage at the I/O pad, thereby ensuring voltages across gates of the PMOS and NMOS transistors to be within a predetermined range.

Abstract: The present disclosure is directed toward electrostatic device protection for semiconductor devices. A circuit for providing electro-static discharge (ESD) protection for a semiconductor circuit may comprise a first circuit coupled to a voltage bus and to the gate of a first transisto, the first circuit comprising a metal-oxide semiconductor (MOS) transistor; and a second circuit coupled to the voltage bus, to ground, and to the gate of the transistor of the first circuit. The MOS transistor of the first circuit may be a PMOS transistor whose source is coupled to the voltage bus, whose drain is coupled to the gate of the first transistor, whose gate is coupled to the second circuit, and whose well is coupled to a floating N-well.

Abstract: A dual-voltage three-state buffer circuit controls a post driver circuit to operate in a three-state mode and includes a tri-state logic control module operated under a low supply voltage, a level shifter for receiving one or more inputs from the tri-state logic control module and operating with an output control circuit for controlling two differential outputs of the level shifter, and a post driver circuit driven by the two differential outputs of the level shifter, wherein the level shifter, the output control circuit, an the post driver circuit are operated under a high supply voltage, and wherein when the tri-state logic control module generates the inputs for putting the post driver circuit in a high impedance state, the output control circuit operates with the level shifter to turn off the PMOS and NMOS transistors of the post driver circuit while isolating the level shifter from a high supply voltage.

Abstract: A tie-high, tie-low circuit having a tie-high output and a tie-low output comprises a regenerative device to be coupled with both the tie-high and the tie-low outputs, and at least a PMOS device and a NMOS device to be coupled respectively with a high voltage and a low voltage. A diode, a NMOS device, and a PMOS device are used as regenerative devices in three examples. These three examples exhibit improved electrostatic discharge (ESD) tolerance.

Abstract: A method is provided for semiconductor ESD protection in a mixed voltage device using a cascaded gate driven NMOS clamp circuit. Use of a bias circuit allows for an external I/O signal to have a voltage higher than the internal circuit power supply voltage so that a proper trigger level is provided in reference to an external power supply reference. A cascaded gate NMOS clamp circuit dissipates charge from an ESD event from the higher external I/O signal level without interfering with the normal operation of the internal or “core” circuits.

Abstract: The invention discloses an integrated circuit that includes a first device in a first power domain; a second device in a second power domain; and an electrostatic discharge (ESD) bus coupled to the first and second devices for providing a current path to dissipate an ESD current during an ESD event occurring at the first or second device. The ESD bus is disposed across the first and second power domains without having a diode module interposed therebetween, thereby preventing the ESD current from flowing through the first and second devices.

Abstract: The present invention discloses an IC implemented with ESD protection system. In one embodiment, the includes a first device in a first power domain, and a second device in a second power domain. A buffer module is coupled between the first device and the second device for allowing a signal to pass across between the first and second devices during a normal operation, and for increasing an impedance between the first and second devices during an electrostatic discharge (ESD) event, thereby reducing a possibility of having an ESD current flow from the first device to the second device.

Abstract: An integrated circuit system includes a first device in a first power domain, and a second device coupled to the first device in a second power domain. A circuit module is coupled between the first device and a power supply voltage or between the first device and a complementary power supply voltage in the first power domain for increasing an impedance against an ESD current flowing from the first device to the second device during an ESD event.

Abstract: A high voltage buffer module used in an input/output buffer circuit coupled between a high voltage circuit and a low voltage circuit, operates between a first supply voltage and its complementary second supply voltage. A pull-up module, coupled between the first supply voltage and an output node, outputs the first supply voltage to the output node, in response to an input signal. A voltage detection circuit provides the pull-up module with at least one bias voltage selected from a predetermined set of voltage levels, wherein the voltage detection circuit selects the bias voltage upon detecting a reduction of the first supply voltage.

Abstract: A power-on control circuit includes a coupling device coupled to a first voltage supply. A first inverter, coupled between the coupling device and a complementary voltage, has an input node coupled to a second voltage supply with a supply voltage level lower than that of the first voltage supply. A level shifter, coupled between the first voltage supply and the complementary voltage, has a first input node connected to an output node of the first inverter and a second input node coupled to the second voltage supply, for generating the power-on control signal when the first voltage supply is powered up and the second voltage supply is turned off and for disabling the power-on control signal when the second voltage supply is subsequently powered up. The coupling device eliminates a leakage current path from the first voltage supply to the complementary voltage through the first inverter.

Abstract: An input buffer for interfacing a high voltage signal received at an input node to a low voltage circuit comprising low voltage devices is provided. The buffer includes a threshold adjustment circuit including an inverter coupled to a threshold adjusted output node. The inverter includes low voltage devices and is coupled between a high supply voltage node and a ground node. The inverter includes a first and second transistors having biasing nodes coupled to a low voltage supply node of the low voltage circuit and coupled to the threshold adjusted output node. The adjustment circuit provides at the threshold adjusted output node an inverted signal corresponding to the high voltage input signal. The buffer also includes a level shifting circuit including low voltage devices and provides a low voltage signal corresponding to the high voltage input signal in response to said inverted signal.

Abstract: An integrated circuit device can be tested using a built-in test circuit, in the IC device, that tests the operation of an I/O cell. The built-in test circuit includes a pattern generator for generating a series of simulation signals. The built-in test circuit successively stores and retrieves the simulation signals from an I/O buffer of the I/O cell. For each iteration of storing and retrieving, test logic of the built-in test circuit compares the stored and retrieved data to check whether the data matches. If a mismatch is detected, the test logic issues a fail signal. The fail signal can cause a unique signal at the pad of the I/O cell that alerts a tester to the failure of the IC device. The fail signal can also cause the issuance of a device failure signal that can be detected at other pins of the IC device.