Abstract: An integrated circuit for level-shifting voltage signals comprising an input/output pad, and an input/output circuit coupled to the output pad having a plurality of devices operating with a bias supply voltage operable to shift between the range of the bias supply voltage to the range of an input/output supply voltage that is higher than the bias supply voltage is provided. In addition, an integrated circuit comprises an input circuit coupled to an input pad operable to input shift signals from an input/output supply voltage range to a core supply voltage range, an output circuit coupled to an output pad operable to shift output signals from a bias supply voltage range to an input/output supply voltage range, and a core circuit coupled to the input and output circuits and having a gate dielectric thickness substantially similar to a gate dielectric thickness of the input circuit and the output circuit.

Abstract: A boost-biased level shifter is described. In the preferred embodiments of the present invention, a voltage divider circuit divides the high voltage applied on the receiver circuit that receives the input signal, a refresh and self-bias circuit maintains and refreshes a bias voltage that is high enough to turn on the transistors in the voltage divider circuit, and a voltage output circuit outputs a signal having the amplitude of a higher power supply source, which is higher than the input signal amplitude. The preferred embodiments can operate at input signals having a lower amplitude. The performance is improved.

Abstract: An input/output buffer comprises an input/output pad operable to receive an input signal and transmit an output signal, an output driver coupled to the input/output pad, an input path comprising an input transistor coupled to the input/output pad operable to pass an input signal received at the input/output pad to a core circuit coupled to the input/output buffer. The input/output buffer further comprises an output path coupled to the output driver operable to pass an output signal received from the core circuit to the input/output pad, a feedback path coupled to the input transistor in the input path and operable to cut off the output path during input mode, and a biasing circuit coupled to selected transistors in the output path, feedback path and output driver.

Abstract: A semiconductor device including a plurality of input/output cells and having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a first pattern, and the at least second bond pads comprise at least one second pattern, wherein the at least one second pattern is different from or the same as the first pattern. Either the first bond pads, the at least second bond pads, or both, may be used to electrically couple the input/output cells of the semiconductor device to leads of an integrated circuit package or other circuit component.

Abstract: I. A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be used for an integrated circuit design, at least one basic cell is selected, the basic cell having a base component for generating the desired I/O cell to meet the configuration requirement. A connection template is generated having one or more programmable connection points identified thereon, the programmable connection points identifying locations for making connections to one or more feature components of the basic cell. The selected basic cell and the connection template are combined to generate a design file, wherein the design file corresponds to the desired I/O cell with the predetermined feature components of the basic cell integrated with the basic component to satisfy the configuration requirement. The disclosed method reduces the design cycle-time as well as circuit-library maintenance and update effort.

Abstract: A tie-high, tie-low circuit having a tie-high output and a tie-low output comprises a regenerative device to be coupled with both the tie-high and the tie-low outputs, and at least a PMOS device and a NMOS device to be coupled respectively with a high voltage and a low voltage. A diode, a NMOS device, and a PMOS device are used as regenerative devices in three examples. These three examples exhibit improved electrostatic discharge (ESD) tolerance.

Abstract: A dual-voltage three-state buffer circuit controls a post driver circuit to operate in a three-state mode and includes a tri-state logic control module operated under a low supply voltage, a level shifter for receiving one or more inputs from the tri-state logic control module and operating with an output control circuit for controlling two differential outputs of the level shifter, and a post driver circuit driven by the two differential outputs of the level shifter, wherein the level shifter, the output control circuit, an the post driver circuit are operated under a high supply voltage, and wherein when the tri-state logic control module generates the inputs for putting the post driver circuit in a high impedance state, the output control circuit operates with the level shifter to turn off the PMOS and NMOS transistors of the post driver circuit while isolating the level shifter from a high supply voltage.

Abstract: In one embodiment, the disclosure relates to a method and apparatus for inter-chip wireless communication system. The system includes a first microprocessor having a plurality of non-contact ports and a first RF communication circuit integrated with the first microprocessor; a second microprocessor also having a plurality of non-contact ports and a second RF communication circuit integrated therein. An RF communication protocol can be configured to receive data from each of the non-contact ports in parallel, multiplex and translate the data to a serial RF signal. Data communication can be accomplished using the wireless communication circuit on each chip. The RF communication between the first and the second integrated circuits using the communication protocol defines a non capacitive-coupling of the first and the second die.

Abstract: An integrated circuit device can be tested using a built-in test circuit, in the IC device, that tests the operation of an I/O cell. The built-in test circuit includes a pattern generator for generating a series of simulation signals. The built-in test circuit successively stores and retrieves the simulation signals from an I/O buffer of the I/O cell. For each iteration of storing and retrieving, test logic of the built-in test circuit compares the stored and retrieved data to check whether the data matches. If a mismatch is detected, the test logic issues a fail signal. The fail signal can cause a unique signal at the pad of the I/O cell that alerts a tester to the failure of the IC device. The fail signal can also cause the issuance of a device failure signal that can be detected at other pins of the IC device.

Abstract: A semiconductor device having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a first pattern, and the at least one second bond pad comprise at least one second pattern, wherein the at least one second pattern is different from or the same as the first pattern. Either the first bond pads, the at least one second bond pad, or both, may be used to electrically couple the input/output cells of the semiconductor device to leads of an integrated circuit package or other circuit component.

Abstract: A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be used for an integrated circuit design, at least one basic cell is selected, the basic cell having a base component for generating the desired I/O cell to meet the configuration requirement. A connection template is generated having one or more programmable connection points identified thereon, the programmable connection points identifying locations for making connections to one or more feature components of the basic cell. The selected basic cell and the connection template are combined to generate a design file, wherein the design file corresponds to the desired I/O cell with the predetermined feature components of the basic cell integrated with the basic component to satisfy the configuration requirement. The disclosed method reduces the design cycle-time as well as circuit-library maintenance and update effort.

Abstract: A high voltage buffer module used in an input/output buffer circuit coupled between a high voltage circuit and a low voltage circuit, operates between a first supply voltage and its complementary second supply voltage. A pull-up module, coupled between the first supply voltage and an output node, outputs the first supply voltage to the output node, in response to an input signal. A voltage detection circuit provides the pull-up module with at least one bias voltage selected from a predetermined set of voltage levels, wherein the voltage detection circuit selects the bias voltage upon detecting a reduction of the first supply voltage.

Abstract: The present disclosure is directed toward electrostatic device protection for semiconductor devices. A circuit for providing electro-static discharge (ESD) protection for a semiconductor circuit may comprise a first circuit coupled to a voltage bus and to the gate of a first transisto, the first circuit comprising a metal-oxide semiconductor (MOS) transistor; and a second circuit coupled to the voltage bus, to ground, and to the gate of the transistor of the first circuit. The MOS transistor of the first circuit may be a PMOS transistor whose source is coupled to the voltage bus, whose drain is coupled to the gate of the first transistor, whose gate is coupled to the second circuit, and whose well is coupled to a floating N-well.

Abstract: An input/output buffer comprises an input/output pad operable to receive an input signal and transmit an output signal, an output driver coupled to the input/output pad, an input path comprising an input transistor coupled to the input/output pad operable to pass an input signal received at the input/output pad to a core circuit coupled to the input/output buffer. The input/output buffer further comprises an output path coupled to the output driver operable to pass an output signal received from the core circuit to the input/output pad, a feedback path coupled to the input transistor in the input path and operable to cut off the output path during input mode, and a biasing circuit coupled to selected transistors in the output path, feedback path and output driver.

Abstract: A boost-biased level shifter is described. In the preferred embodiments of the present invention, a voltage divider circuit divides the high voltage applied on the receiver circuit that receives the input signal, a refresh and self-bias circuit maintains and refreshes a bias voltage that is high enough to turn on the transistors in the voltage divider circuit, and a voltage output circuit outputs a signal having the amplitude of a higher power supply source, which is higher than the input signal amplitude. The preferred embodiments can operate at input signals having a lower amplitude. The performance is improved.

Abstract: A method is provided for semiconductor ESD protection in a mixed voltage device using a cascaded gate driven NMOS clamp circuit. Use of a bias circuit allows for an external I/O signal to have a voltage higher than the internal circuit power supply voltage so that a proper trigger level is provided in reference to an external power supply reference. A cascaded gate NMOS clamp circuit dissipates charge from an ESD event from the higher external I/O signal level without interfering with the normal operation of the internal or “core” circuits.

Abstract: An input buffer for interfacing a high voltage signal received at an input node to a low voltage circuit comprising low voltage devices is provided. The buffer includes a threshold adjustment circuit including an inverter coupled to a threshold adjusted output node. The inverter includes low voltage devices and is coupled between a high supply voltage node and a ground node. The inverter includes a first and second transistors having biasing nodes coupled to a low voltage supply node of the low voltage circuit and coupled to the threshold adjusted output node. The adjustment circuit provides at the threshold adjusted output node an inverted signal corresponding to the high voltage input signal. The buffer also includes a level shifting circuit including low voltage devices and provides a low voltage signal corresponding to the high voltage input signal in response to said inverted signal.

Abstract: A semiconductor device having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a first pattern, and the at least one second bond pad comprise at least one second pattern, wherein the at least one second pattern is different from or the same as the first pattern. Either the first bond pads, the at least one second bond pad, or both, may be used to electrically couple the input/output cells of the semiconductor device to leads of an integrated circuit package or other circuit component.

Abstract: A physical layer of a USB interface. A test signal generator generates a test signal. A signal sampling device coupled to the test signal generator samples the test signal and outputs the test signal after a predetermined time. A transmitter and a receiver coupled to a signal access the data of the transmission terminals. A USB transceiver macrocell coupled to the test signal generator, the transmitter and receiver converts the test signal to USB protocol, outputs a first converted signal through the transmitter, receives the first converted signal through the transmission terminals and the receiver, and converts the received first converted signal to a second converted signal. A comparator coupled to the USB transceiver macrocell and the signal sampling device compares the second converted signal with the test signal, and outputs an error acknowledging signal.

Abstract: A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be used for an integrated circuit design, at least one basic cell is selected, the basic cell having a base component for generating the desired I/O cell to meet the configuration requirement. A connection template is generated having one or more programmable connection points identified thereon, the programmable connection points identifying locations for making connections to one or more feature components of the basic cell. The selected basic cell and the connection template are combined to generate a design file, wherein the design file corresponds to the desired I/O cell with the predetermined feature components of the basic cell integrated with the basic component to satisfy the configuration requirement. The disclosed method reduces the design cycle-time as well as circuit-library maintenance and update effort.