Abstract: One illustrative method disclosed herein includes, among other things, oxidizing a lower portion of an initial fin structure to thereby define an isolation region that vertically separates an upper portion of the initial fin structure from a semiconducting substrate, performing a recess etching process to remove a portion of the upper portion of the initial fin structure so as to define a recessed fin portion, forming a replacement fin on the recessed fin portion so as to define a final fin structure comprised of the replacement fin and the recessed fin portion, and forming a gate structure around at least a portion of the replacement fin.

Abstract: Forming a plurality of initial trenches that extend through a layer of silicon-germanium and into a substrate to define an initial fin structure comprised of a portion of the layer of germanium-containing material and a first portion of the substrate, forming sidewall spacers adjacent the initial fin structure, performing an etching process to extend the initial depth of the initial trenches, thereby forming a plurality of final trenches having a final depth that is greater than the initial depth and defining a second portion of the substrate positioned under the first portion of the substrate, forming a layer of insulating material over-filling the final trenches and performing a thermal anneal process to convert at least a portion of the first or second portions of the substrate into a silicon dioxide isolation material that extends laterally under an entire width of the portion of the germanium-containing material.

Abstract: One illustrative device disclosed herein includes a fin defined in a semiconductor substrate having a crystalline structure, wherein at least a sidewall of the fin is positioned substantially in a <100> crystallographic direction of the substrate, a gate structure positioned around the fin, an outermost sidewall spacer positioned adjacent opposite sides of the gate structure, and an epi semiconductor material formed around portions of the fin positioned laterally outside of the outermost sidewall spacers in the source/drain regions of the device, wherein the epi semiconductor material has a substantially uniform thickness along the sidewalls of the fin.

Abstract: Forming a plurality of initial trenches that extend through a layer of silicon-germanium and into a substrate to define an initial fin structure comprised of a portion of the layer of germanium-containing material and a first portion of the substrate, forming sidewall spacers adjacent the initial fin structure, performing an etching process to extend the initial depth of the initial trenches, thereby forming a plurality of final trenches having a final depth that is greater than the initial depth and defining a second portion of the substrate positioned under the first portion of the substrate, forming a layer of insulating material over-filling the final trenches and performing a thermal anneal process to convert at least a portion of the first or second portions of the substrate into a silicon dioxide isolation material that extends laterally under an entire width of the portion of the germanium-containing material.

Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.

Abstract: Fin field effect transistor integrated circuits and methods for producing the same are provided. A fin field effect transistor integrated circuit includes a plurality of fins extending from a semiconductor substrate. Each of the plurality of fins includes a fin sidewall, and each of the plurality of fins extends to a fin height such that a trough with a trough base is defined between adjacent fins. A second dielectric is positioned within the trough, where the second dielectric directly contacts the semiconductor substrate at the trough base. The second dielectric extends to a second dielectric height less than the fin height such that protruding fin portions extend above the second dielectric. A first dielectric is positioned between the fin sidewall and the second dielectric.

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

Abstract: are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques.

Abstract: Methods for fabricating integrated circuits and FinFET transistors on bulk substrates with active channel regions isolated from the substrate with an insulator are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end. The method deposits an anchoring material over the fin structures. The method includes recessing the anchoring material to form trenches adjacent the fin structures, wherein the anchoring material remains in contact with the first end and the second end of each fin structure. Further, the method forms a void between the semiconductor substrate and the channel material of each fin structure with a gate length independent etching process, wherein the channel material of each fin structure is suspended over the semiconductor substrate.

Abstract: A fin field effect transistor integrated circuit (FinFET IC) has a plurality of fins extending from a semiconductor substrate, where a trough is defined between adjacent fins. A second dielectric is positioned within the trough, and a protruding portion of the fins extends above the second dielectric. A first dielectric is positioned between the fin sidewalls and the second dielectric.

Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.

Abstract: Methods for fabricating integrated circuits and FinFET transistors on bulk substrates with active channel regions isolated from the substrate with an insulator are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end. The method deposits an anchoring material over the fin structures. The method includes recessing the anchoring material to form trenches adjacent the fin structures, wherein the anchoring material remains in contact with the first end and the second end of each fin structure. Further, the method forms a void between the semiconductor substrate and the channel material of each fin structure with a gate length independent etching process, wherein the channel material of each fin structure is suspended over the semiconductor substrate.

Abstract: Semiconductor structures and fabrication methods are provided integrating different fin device architectures on a common wafer, for instance, within a common functional device area of the wafer. The method includes: facilitating fabricating multiple fin device architectures within a common functional device wafer area by: providing a wafer with at least one fin disposed over a substrate, the fin including an isolation layer; modifying the fin(s) in a first region of the fin(s), while protecting the fin in a second region of the fin(s); and proceeding with forming one or more fin devices of a first architectural type in the first region and one or more fin devices of a second architectural type in the second region. The first architectural type and the second architectural type are different fin device architectures, such as different fin device isolation architectures, different fin type transistor architectures, or different fin-type devices or structures.

Abstract: A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source and a vertically elongated drain. The stack includes a top channel region and a dielectric region immediately below the channel region, providing electrical isolation of the channel. The partial isolation structure can be used with both gate first and gate last fabrication processes.

Abstract: A semiconductor stack of a FinFET in fabrication includes a bulk silicon substrate, a selectively oxidizable sacrificial layer over the bulk substrate and an active silicon layer over the sacrificial layer. Fins are etched out of the stack of active layer, sacrificial layer and bulk silicon. A conformal oxide deposition is made to encapsulate the fins, for example, using a HARP deposition. Relying on the sacrificial layer having a comparatively much higher oxidation rate than the active layer or substrate, selective oxidization of the sacrificial layer is performed, for example, by annealing. The presence of the conformal oxide provides structural stability to the fins, and prevents fin tilting, during oxidation. Selective oxidation of the sacrificial layer provides electrical isolation of the top active silicon layer from the bulk silicon portion of the fin, resulting in an SOI-like structure. Further fabrication may then proceed to convert the active layer to the source, drain and channel of the FinFET.

Abstract: A fin field effect transistor integrated circuit (FinFET IC) has a plurality of fins extending from a semiconductor substrate, where a trough is defined between adjacent fins. A second dielectric is positioned within the trough, and a protruding portion of the fins extends above the second dielectric. A first dielectric is positioned between the fin sidewalls and the second dielectric.

Abstract: Aspects of the present invention relate to an approach for forming an integrated circuit having a set of fins on a silicon substrate, with the set of fins being formed according to a predetermined pattern. In situ doping of the fins with an N-type dopant prior to deposition of an epitaxial layer minimizes punch through leakage whilst an epitaxial depositional process applies a cladding layer on the doped fins, the deposition resulting in a multigate device having improved device isolation.

Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.

Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.