Patents by Inventor Kerem Akarvardar

Kerem Akarvardar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9117875
    Abstract: Forming a plurality of initial trenches that extend through a layer of silicon-germanium and into a substrate to define an initial fin structure comprised of a portion of the layer of germanium-containing material and a first portion of the substrate, forming sidewall spacers adjacent the initial fin structure, performing an etching process to extend the initial depth of the initial trenches, thereby forming a plurality of final trenches having a final depth that is greater than the initial depth and defining a second portion of the substrate positioned under the first portion of the substrate, forming a layer of insulating material over-filling the final trenches and performing a thermal anneal process to convert at least a portion of the first or second portions of the substrate into a silicon dioxide isolation material that extends laterally under an entire width of the portion of the germanium-containing material.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: August 25, 2015
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Jody A. Fronheiser, Kangguo Cheng, Bruce Doris, Kern Rim
  • Publication number: 20150214369
    Abstract: One illustrative device disclosed herein includes a fin defined in a semiconductor substrate having a crystalline structure, wherein at least a sidewall of the fin is positioned substantially in a <100> crystallographic direction of the substrate, a gate structure positioned around the fin, an outermost sidewall spacer positioned adjacent opposite sides of the gate structure, and an epi semiconductor material formed around portions of the fin positioned laterally outside of the outermost sidewall spacers in the source/drain regions of the device, wherein the epi semiconductor material has a substantially uniform thickness along the sidewalls of the fin.
    Type: Application
    Filed: January 27, 2014
    Publication date: July 30, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jody A. Fronheiser, Bharat V. Krishnan, Murat Kerem Akarvardar, Steven Bentley, Ajey Poovannummoottil Jacob, Jinping Liu
  • Publication number: 20150200128
    Abstract: Forming a plurality of initial trenches that extend through a layer of silicon-germanium and into a substrate to define an initial fin structure comprised of a portion of the layer of germanium-containing material and a first portion of the substrate, forming sidewall spacers adjacent the initial fin structure, performing an etching process to extend the initial depth of the initial trenches, thereby forming a plurality of final trenches having a final depth that is greater than the initial depth and defining a second portion of the substrate positioned under the first portion of the substrate, forming a layer of insulating material over-filling the final trenches and performing a thermal anneal process to convert at least a portion of the first or second portions of the substrate into a silicon dioxide isolation material that extends laterally under an entire width of the portion of the germanium-containing material.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 16, 2015
    Applicants: International Business Machines Corporation, Globalfoundries Inc.
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Jody A. Fronheiser, Kangguo Cheng, Bruce Doris, Kern Rim
  • Patent number: 9076842
    Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: July 7, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Steven John Bentley, Bartlomiej Jan Pawlak
  • Publication number: 20150179644
    Abstract: Fin field effect transistor integrated circuits and methods for producing the same are provided. A fin field effect transistor integrated circuit includes a plurality of fins extending from a semiconductor substrate. Each of the plurality of fins includes a fin sidewall, and each of the plurality of fins extends to a fin height such that a trough with a trough base is defined between adjacent fins. A second dielectric is positioned within the trough, where the second dielectric directly contacts the semiconductor substrate at the trough base. The second dielectric extends to a second dielectric height less than the fin height such that protruding fin portions extend above the second dielectric. A first dielectric is positioned between the fin sidewall and the second dielectric.
    Type: Application
    Filed: February 6, 2015
    Publication date: June 25, 2015
    Inventors: Murat Kerem Akarvardar, Xiuyu Cai, Ajey Poovannummoottil Jacob
  • Publication number: 20150137308
    Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicants: International Business Machines Corporation, Renesas Electronics Corporation, GLOBALFOUNDRIES Inc.
    Inventors: Murat Kerem Akarvardar, Steven John Bentley, Kangguo Cheng, Bruce B. Doris, Jody Fronheiser, Ajey Poovannummoottil Jacob, Ali Khakifirooz, Toshiharu Nagumo
  • Publication number: 20150140761
    Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.
    Type: Application
    Filed: January 19, 2015
    Publication date: May 21, 2015
    Applicants: GLOBALFOUNDRIES INC., International Business Machines Corporation, Renesas Electronics Corporation
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Steven Bentley, Toshiharu Nagumo, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz
  • Publication number: 20150123166
    Abstract: are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Michael Hargrove, Ruilong Xie
  • Patent number: 9006077
    Abstract: Methods for fabricating integrated circuits and FinFET transistors on bulk substrates with active channel regions isolated from the substrate with an insulator are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end. The method deposits an anchoring material over the fin structures. The method includes recessing the anchoring material to form trenches adjacent the fin structures, wherein the anchoring material remains in contact with the first end and the second end of each fin structure. Further, the method forms a void between the semiconductor substrate and the channel material of each fin structure with a gate length independent etching process, wherein the channel material of each fin structure is suspended over the semiconductor substrate.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: April 14, 2015
    Assignee: GlobalFoundries, Inc.
    Inventors: Murat Kerem Akarvardar, Ajey Poovannummoottil Jacob
  • Patent number: 8987094
    Abstract: A fin field effect transistor integrated circuit (FinFET IC) has a plurality of fins extending from a semiconductor substrate, where a trough is defined between adjacent fins. A second dielectric is positioned within the trough, and a protruding portion of the fins extends above the second dielectric. A first dielectric is positioned between the fin sidewalls and the second dielectric.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: March 24, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Murat Kerem Akarvardar, Xiuyu Cai, Ajey Poovannummoottil Jacob
  • Publication number: 20150061014
    Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil JACOB, Murat Kerem AKARVARDAR, Steven John BENTLEY, Bartlomiej Jan PAWLAK
  • Publication number: 20150056781
    Abstract: Methods for fabricating integrated circuits and FinFET transistors on bulk substrates with active channel regions isolated from the substrate with an insulator are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end. The method deposits an anchoring material over the fin structures. The method includes recessing the anchoring material to form trenches adjacent the fin structures, wherein the anchoring material remains in contact with the first end and the second end of each fin structure. Further, the method forms a void between the semiconductor substrate and the channel material of each fin structure with a gate length independent etching process, wherein the channel material of each fin structure is suspended over the semiconductor substrate.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 26, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Murat Kerem Akarvardar, Ajey Poovannummoottil Jacob
  • Publication number: 20150021709
    Abstract: Semiconductor structures and fabrication methods are provided integrating different fin device architectures on a common wafer, for instance, within a common functional device area of the wafer. The method includes: facilitating fabricating multiple fin device architectures within a common functional device wafer area by: providing a wafer with at least one fin disposed over a substrate, the fin including an isolation layer; modifying the fin(s) in a first region of the fin(s), while protecting the fin in a second region of the fin(s); and proceeding with forming one or more fin devices of a first architectural type in the first region and one or more fin devices of a second architectural type in the second region. The first architectural type and the second architectural type are different fin device architectures, such as different fin device isolation architectures, different fin type transistor architectures, or different fin-type devices or structures.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 22, 2015
    Inventors: Ajey P. JACOB, Murat Kerem AKARVARDAR, Michael John HARGROVE
  • Publication number: 20150021663
    Abstract: A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source and a vertically elongated drain. The stack includes a top channel region and a dielectric region immediately below the channel region, providing electrical isolation of the channel. The partial isolation structure can be used with both gate first and gate last fabrication processes.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 22, 2015
    Inventors: Murat Kerem AKARVARDAR, Jody A. Fronheiser, Ajey Poovannummoottil JACOB
  • Publication number: 20150021691
    Abstract: A semiconductor stack of a FinFET in fabrication includes a bulk silicon substrate, a selectively oxidizable sacrificial layer over the bulk substrate and an active silicon layer over the sacrificial layer. Fins are etched out of the stack of active layer, sacrificial layer and bulk silicon. A conformal oxide deposition is made to encapsulate the fins, for example, using a HARP deposition. Relying on the sacrificial layer having a comparatively much higher oxidation rate than the active layer or substrate, selective oxidization of the sacrificial layer is performed, for example, by annealing. The presence of the conformal oxide provides structural stability to the fins, and prevents fin tilting, during oxidation. Selective oxidation of the sacrificial layer provides electrical isolation of the top active silicon layer from the bulk silicon portion of the fin, resulting in an SOI-like structure. Further fabrication may then proceed to convert the active layer to the source, drain and channel of the FinFET.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 22, 2015
    Inventors: Murat Kerem AKARVARDAR, Jody A. FRONHEISER, Ajey Poovannummoottil JACOB
  • Publication number: 20150014776
    Abstract: A fin field effect transistor integrated circuit (FinFET IC) has a plurality of fins extending from a semiconductor substrate, where a trough is defined between adjacent fins. A second dielectric is positioned within the trough, and a protruding portion of the fins extends above the second dielectric. A first dielectric is positioned between the fin sidewalls and the second dielectric.
    Type: Application
    Filed: July 9, 2013
    Publication date: January 15, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Murat Kerem Akarvardar, Xiuyu Cai, Ajey Poovannummoottil Jacob
  • Publication number: 20140374807
    Abstract: Aspects of the present invention relate to an approach for forming an integrated circuit having a set of fins on a silicon substrate, with the set of fins being formed according to a predetermined pattern. In situ doping of the fins with an N-type dopant prior to deposition of an epitaxial layer minimizes punch through leakage whilst an epitaxial depositional process applies a cladding layer on the doped fins, the deposition resulting in a multigate device having improved device isolation.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Bruce B. Doris, Ali Khakifirooz
  • Publication number: 20140361377
    Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 11, 2014
    Inventors: Ajey Poovannummoottil Jacob, Steven John Bentley, Murat Kerem Akarvardar, Jody Alan Fronheiser, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Toshiharu Nagumo
  • Patent number: 8853019
    Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jody A. Fronheiser, Jeremy A. Wahl, Kerem Akarvardar, Ajey P. Jacob, Daniel T. Pham
  • Publication number: 20140264488
    Abstract: One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a <100> crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the substrate fin, wherein the replacement fin structure is comprised of a semiconductor material that is different from the first semiconductor material, and a gate structure positioned around at least a portion of the replacement fin structure.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Jody Fronheiser, Ajey P. Jacob, Witold P. Maszara, Kerem Akarvardar