Abstract: One illustrative method disclosed herein includes, among other things, performing first and second in situ doping, epitaxial deposition processes to form first and second layers of in situ doped epi semiconductor material, respectively, above a semiconductor substrate, wherein one of the first and second layers has a high level of germanium and a low level of P-type dopant material and the other of the first and second layers has a low level of germanium and a high level of P-type dopant material, and performing a mixing thermal anneal process on the first and second layers so as to form the final silicon germanium material having a high level of germanium and a high level of P-type dopant material.

Abstract: One illustrative method disclosed herein includes, among other things, forming a layer of insulating material in the source/drain regions of the device, wherein the layer of insulating material has an upper surface that is substantially planar with an upper surface of a gate cap layer, recessing the layer of insulating material such that its recessed upper surface exposes a surface of the fin, performing another etching process to remove at least a portion of the fin and thereby define a recessed fin trench positioned above the recessed fin, and forming an epitaxial semiconductor material that is at least partially positioned in the recessed fin trench.

Abstract: Reducing a chance of punch-through in a FinFET structure includes providing a substrate, creating a blanket layer of semiconductor material with impurities therein over the substrate, masking a portion of the blanket layer, creating epitaxial semiconductor material on an unmasked portion of the structure, removing the mask, and etching the structure to create n-type raised structure(s) and p-type raised structure(s), a bottom portion of the raised structure(s) being surrounded by isolation material. A middle portion of the raised structure(s) includes a semiconductor material with impurities therein, the middle portion extending across the raised structure(s), and a top portion including a semiconductor material lacking added impurities.

Abstract: Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of initial fins that have the same initial axial length and the same initial strain above a substrate, performing at least one etching process so as to cut a first fin to a first axial length and to cut a second fin to a second axial length that is less than the first axial length, wherein the cut first fin retains a first amount of the initial strain and the cut second fin retains about zero of the initial strain or a second amount of the initial strain that is less than the first amount, and forming gate structures around the first and second cut fins to form FinFET devices.

Abstract: There is set forth herein a method including patterning a fin on a substrate of a semiconductor structure, forming dielectric material over the substrate, performing a process for removing material from a fin to define a cavity at a channel region of the fin, and forming a replacement semiconductor material formation at the channel region.

Abstract: One illustrative method disclosed herein includes forming a recessed fin structure and a replacement fin cavity in a layer of insulating material above the recessed fin structure, forming at least first and second individual layers of epi semiconductor material in the replacement fin cavity, wherein each of the first and second layers have different concentrations of germanium, performing an anneal process on the first and second layers so as to form a substantially homogeneous SiGe replacement fin in the fin cavity, and forming a gate structure around at least a portion of the replacement fin.

Abstract: One illustrative method disclosed herein includes, among other things, oxidizing a lower portion of an initial fin structure to thereby define an isolation region that vertically separates an upper portion of the initial fin structure from a semiconducting substrate, performing a recess etching process to remove a portion of the upper portion of the initial fin structure so as to define a recessed fin portion, forming a replacement fin on the recessed fin portion so as to define a final fin structure comprised of the replacement fin and the recessed fin portion, and forming a gate structure around at least a portion of the replacement fin.

Abstract: One illustrative method disclosed herein includes, among other things, forming at least one layer of insulating material with a substantially planar upper surface that is positioned above the upper surface of the fin, forming a layer of sacrificial gate material on the layer of insulating material, the layer of sacrificial gate material having an as-deposited upper surface and a substantially uniform thickness, forming a layer of gate cap material on the as-deposited upper surface of the layer of sacrificial gate material, forming a patterned sacrificial gate structure comprised of at least the gate cap material and the sacrificial gate material, forming a sidewall spacer adjacent the patterned sacrificial gate structure, removing the patterned sacrificial gate structure and replacing it with a replacement gate structure.

Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an NMOS FinFET device.

Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.

Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

Abstract: Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion, the upper fin portion including a sacrificial material; forming a gate structure over the fin; selectively removing the upper fin portion to form a tunnel between the gate structure and lower fin portion; and providing a channel material in the tunnel to define the channel region of the gate structure. The sacrificial material may be a material that can be selectively etched without etching the material of the lower fin portion. The channel material may further be provided to form source and drain regions of the transistor structure, which may result in a junctionless FinFET structure.

Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure comprised of a sacrificial silicon material and a first non-sacrificial semiconductor material positioned above the sacrificial silicon material, forming a second non-sacrificial semiconductor material in each of the trenches adjacent the composite fin structure, performing at least one etching process so as to cut the composite fin structure and thereby expose cut end surfaces of the sacrificial silicon material, selectively removing the sacrificial silicon material of the composite fin structure relative to the first and second non-sacrificial semiconductor materials and forming a layer of strained channel semiconductor material above an upper surface of the first non-sacrificial semiconductor material of the composite fin structure and above an upper surface of the second non-sacrificial semiconductor materials positioned in the trenches.

Abstract: The present disclosure is directed to forming relatively abrupt junctions between the channel region and source/drain regions of a PMOS transistor device with a germanium-containing channel region. A liner layer is formed in previously formed source/drain cavities prior to the formation of epi semiconductor material in the source/drain cavities above the liner layer. The materials for the liner layer and, particularly, the concentration of germanium (if any is present) are adjusted relative to the germanium concentration in the channel region and the epi source/drain material such that, during an anneal process, dopant materials (e.g., boron) that diffuse from the source/drain region during the anneal process tend to accumulate in or near the liner layer.

Abstract: One illustrative method disclosed herein includes, among other things, forming at least one layer of insulating material with a substantially planar upper surface that is positioned above the upper surface of the fin, forming a layer of sacrificial gate material on the layer of insulating material, the layer of sacrificial gate material having an as-deposited upper surface and a substantially uniform thickness, forming a layer of gate cap material on the as-deposited upper surface of the layer of sacrificial gate material, forming a patterned sacrificial gate structure comprised of at least the gate cap material and the sacrificial gate material, forming a sidewall spacer adjacent the patterned sacrificial gate structure, removing the patterned sacrificial gate structure and replacing it with a replacement gate structure.

Abstract: A method of creating a virtual relaxed substrate includes providing a bulk semiconductor substrate, and creating a layer of strained semiconductor material on the substrate, a non-zero lattice mismatch of less than about 2% being present between the substrate and the layer of strained semiconductor material, and the layer of strained semiconductor material having a thickness of from about 50 nm to about 150 nm. The method further includes etching through the layer of strained semiconductor material and into the substrate to create shaped pillars separated by slits and sized to achieve edge effect relaxation throughout each shaped pillar, merging a top portion of the pillars with single crystal growth of epitaxial material to create a continuous surface while substantially maintaining the slits, and creating a virtual relaxed substrate by creating a layer of epitaxial composite semiconductor material over the continuous surface.

Abstract: One illustrative method disclosed herein includes, among other things, performing first and second in situ doping, epitaxial deposition processes to form first and second layers of in situ doped epi semiconductor material, respectively, above a semiconductor substrate, wherein one of the first and second layers has a high level of germanium and a low level of P-type dopant material and the other of the first and second layers has a low level of germanium and a high level of P-type dopant material, and performing a mixing thermal anneal process on the first and second layers so as to form the final silicon germanium material having a high level of germanium and a high level of P-type dopant material.

Abstract: One illustrative method includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a substrate fin, forming a layer of insulating material in the trenches, and forming a layer of CTE-matching material above the upper surface of the layer of insulating material, wherein the layer of CTE-matching material has a CTE that is within ±20% of the replacement fin CTE and wherein the layer of CTE-matching material partially defines a replacement fin cavity that exposes an upper portion of the substrate fin. In this example, the method also includes forming the replacement fin on the substrate fin and in the replacement fin cavity, removing the layer of CTE-matching material and forming a gate structure around at least a portion of the replacement fin.