Patents by Inventor Kerry Bernstein

Kerry Bernstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HYBRID CRYSTAL ORIENTATION CMOS STRUCTURE FOR ADAPTIVE WELL BIASING AND FOR POWER AND PERFORMANCE ENHANCEMENT
    Publication number: 20080009114
    Abstract: The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.
    Type: Application
    Filed: September 24, 2007
    Publication date: January 10, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kerry Bernstein, Jeffrey Sleight, Min Yang
  • STRUCTURE COMPRISING 3-DIMENSIONAL INTEGRATED CIRCUIT ARCHITECTURE, CIRCUIT STRUCTURE, AND INSTRUCTIONS FOR FABRICATION THEREOF
    Publication number: 20070283298
    Abstract: A design structure comprising an integrated circuit architecture, circuit structure, and/or instructions for fabrication thereof. The circuit structure includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.
    Type: Application
    Filed: June 26, 2007
    Publication date: December 6, 2007
    Inventors: Kerry Bernstein, Paul Coteus, Philip Emma
  • DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS
    Publication number: 20070267723
    Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
    Type: Application
    Filed: May 16, 2006
    Publication date: November 22, 2007
    Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
  • DUAL-SIDED CHIP ATTACHED MODULES
    Publication number: 20070267746
    Abstract: An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.
    Type: Application
    Filed: May 16, 2006
    Publication date: November 22, 2007
    Inventors: Kerry Bernstein, Timothy Dalton, Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Mark David Jaffe, Christopher David Muzzy, Wolfgang Sauter, Edmund Sprogis, Anthony Kendall Stamper
  • DUAL WIRED INTEGRATED CIRCUIT CHIPS
    Publication number: 20070267698
    Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.
    Type: Application
    Filed: July 9, 2007
    Publication date: November 22, 2007
    Inventors: Kerry Bernstein, Timothy Dalton, Jeffrey Gambino, Mark Jaffe, Paul Kartschoke, Anthony Stamper
  • Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability
    Patent number: 7298161
    Abstract: A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: November 20, 2007
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Ronald J. Bolam, Edward J. Nowak, Alvin W. Strong, Jody J. Van Horn, Ernest Y. Wu
  • THREE-DIMENSIONAL NETWORKING STRUCTURE
    Publication number: 20070266129
    Abstract: Disclosed herein is a multi-layer silicon stack architecture including: one or more processing layers including one or more computing elements; one or more networking layers disposed between the processing layers, the network layer includes one or more networking elements, wherein each computing element includes a plurality of network connections to adjacently disposed networking elements.
    Type: Application
    Filed: May 12, 2006
    Publication date: November 15, 2007
    Applicant: International Business Machines Corporation
    Inventors: Kerry Bernstein, Timothy Dalton, Marc Faucher, Peter Sandon
  • DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE
    Publication number: 20070258305
    Abstract: A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.
    Type: Application
    Filed: April 13, 2006
    Publication date: November 8, 2007
    Inventors: Kerry Bernstein, Kenneth Goodnow, Clarence Ogilvie, Sebastian Ventrone, Keith Williams
  • Dual wired integrated circuit chips
    Patent number: 7285477
    Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: October 23, 2007
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
  • DETERMINING HISTORY STATE OF DATA IN DATA RETAINING DEVICE BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR
    Publication number: 20070242507
    Abstract: A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.
    Type: Application
    Filed: April 12, 2006
    Publication date: October 18, 2007
    Inventors: Kerry Bernstein, Kenneth Goodnow, Clearence Ogilvis, Sebastian Ventrone, Kelth Williams
  • METHOD AND ARCHITECTURE FOR POWER MANAGEMENT OF AN ELECTRONIC DEVICE
    Publication number: 20070228830
    Abstract: A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more switches.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Inventors: Kerry Bernstein, Kenneth Goodnow, Clarence Ogilvie, Keith Williams, Sebastian Ventrone
  • 3-DIMENSIONAL INTEGRATED CIRCUIT ARCHITECTURE, STRUCTURE AND METHOD FOR FABRICATION THEREOF
    Publication number: 20070228383
    Abstract: An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Inventors: Kerry Bernstein, Paul Coteus, Philip Emma
  • Intralevel decoupling capacitor, method of manufacture and testing circuit of the same
    Publication number: 20070204447
    Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
    Type: Application
    Filed: February 16, 2007
    Publication date: September 6, 2007
    Applicant: International Business Machines Corporation
    Inventors: Kerry Bernstein, John Bracchitta, William Cote, Tak Ning, Wilbur Pricer
  • BEOL compatible FET structure
    Publication number: 20070194450
    Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.
    Type: Application
    Filed: February 21, 2006
    Publication date: August 23, 2007
    Inventors: Christy Tyberg, Katherine Saenger, Jack Chu, Harold Hovel, Robert Wisnieff, Kerry Bernstein, Stephen Bedell
  • PROCESSOR PIPELINE ARCHITECTURE LOGIC STATE RETENTION SYSTEMS AND METHODS
    Publication number: 20070198808
    Abstract: A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.
    Type: Application
    Filed: February 20, 2006
    Publication date: August 23, 2007
    Inventors: Kerry Bernstein, Kenneth Goodnow, Clarence Ogilvie, Christopher Reynolds, Sebastian Ventrone, Keith Williams
  • SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and method for making same
    Patent number: 7217978
    Abstract: The present invention generally concerns fabrication methods and device architectures for use in memory circuits, and more particularly concerns hybrid silicon-on-insulator (SOI) and bulk architectures for use in memory circuits. Once aspect of the invention concerns CMOS SRAM cell architectures where at least one pair of adjacent NFETs in an SRAM cell have body regions linked by a leakage path diffusion region positioned beneath shallow source/drain diffusions, where the leakage path diffusion region extends from the bottom of the source/drain diffusion to the buried oxide layer, and at least one pair of NFETs from adjacent SRAM cells which have body regions linked by a similar leakage path diffusion region beneath adjacent source/drain diffusions.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: May 15, 2007
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Richard Andre Wachnik, Yue Tan, Kerry Bernstein
  • WAFER LEVEL I/O TEST AND REPAIR ENABLED BY I/O LAYER
    Publication number: 20070081410
    Abstract: A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
    Type: Application
    Filed: October 7, 2005
    Publication date: April 12, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kerry Bernstein, Paul Coteus, Ibrahim Elfadel, Philip Emma, Daniel Friedman, Ruchir Puri, Mark Ritter, Jeannine Trewhella, Albert Young
  • Method of manufacturing an intralevel decoupling capacitor
    Patent number: 7195971
    Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: March 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, John A. Bracchitta, William J. Cote, Tak H. Ning, Wilbur D. Pricer
  • FinFETs with long gate length at high density
    Patent number: 7183142
    Abstract: A method of manufacturing fin-type field effect transistors (FinFETs) forms a silicon layer above a substrate, forms a mask pattern above the silicon layer using a multi-step mask formation process, patterns the silicon layer into silicon fins using the mask pattern such that the silicon fins only remain below the mask pattern, removes the mask pattern to leave the fins on the substrate, and forms gate conductors over the fins at a non-perpendicular angle to the fins.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: February 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Kerry Bernstein, Edward J. Nowak
  • FinFET TRANSISTOR AND CIRCUIT
    Publication number: 20060255410
    Abstract: A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.
    Type: Application
    Filed: July 18, 2006
    Publication date: November 16, 2006
    Inventors: Kerry Bernstein, Edward Nowak, BethAnn Rainey