Patents by Inventor Kerry Bernstein

Kerry Bernstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • 3-DIMENSIONAL INTEGRATED CIRCUIT ARCHITECTURE, STRUCTURE AND METHOD FOR FABRICATION THEREOF
    Publication number: 20080259671
    Abstract: An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.
    Type: Application
    Filed: May 27, 2008
    Publication date: October 23, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kerry Bernstein, Paul W. Coteus, Philip G. Emma
  • DUAL WIRED INTEGRATED CIRCUIT CHIPS
    Publication number: 20080213948
    Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.
    Type: Application
    Filed: February 12, 2008
    Publication date: September 4, 2008
    Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
  • Three-Dimensional Cascaded Power Distribution in a Semiconductor Device
    Publication number: 20080203445
    Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.
    Type: Application
    Filed: May 15, 2008
    Publication date: August 28, 2008
    Applicant: International Business Machines Corporation
    Inventors: Kerry Bernstein, Paul W. Coteus, Philip George Emma, Allan Mark Hartstein, Stephen V. Kosonocky, Ruchir Puri, Mark B. Ritter
  • SYSTEM AND METHOD FOR DESIGNING A LOW LEAKAGE MONOTONIC CMOS LOGIC CIRCUIT
    Publication number: 20080195987
    Abstract: A computer system for designing a low leakage monotonic CMOS logic circuit. The system performing the computer implements steps of: (a) specifying a reference PFET having its threshold voltage and its gate dielectric thickness and a reference NFET having its threshold voltage and its gate dielectric thickness; (b) synthesizing a schematic circuit design with standard design elements, the standard design elements including one or more reference PFETS and one or more reference NFETs; (c) analyzing one or more circuits for logic stages having predominantly high input logic states or predominantly low input logic states; (d) selecting one or more logic stages determined to have predominantly high input logic states or predominantly low input logic states; and (e) replacing the standard design elements of the selected logic stages with reduced current leakage elements.
    Type: Application
    Filed: April 15, 2008
    Publication date: August 14, 2008
    Inventors: Kerry Bernstein, Norman J. Rohrer
  • 3-dimensional integrated circuit architecture, structure and method for fabrication thereof
    Patent number: 7408798
    Abstract: An integrated circuit design, structure and method for fabrication Thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: August 5, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Paul W. Coteus, Philip G. Emma
  • Three-dimensional cascaded power distribution in a semiconductor device
    Patent number: 7402854
    Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: July 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Paul W. Coteus, Philip George Emma, Allan Mark Hartstein, Stephen V. Kosonocky, Ruchir Puri, Mark B. Ritter
  • THREE-DIMENSIONAL ARCHITECTURE FOR SELF-CHECKING AND SELF-REPAIRING INTEGRATED CIRCUITS
    Publication number: 20080165521
    Abstract: A three-dimensional architecture chip includes a base chip including a unit integrated thereon and configured to perform electrical signal operations. An active layer is separately fabricated from the base layer. The active layer includes a component to service the unit of the base chip. The active layer is bonded to the base chip such that the component is aligned in vertical proximity of the unit. An electrical connection connects the unit to the component through vertical layers of at least one of the base chip and the active layer.
    Type: Application
    Filed: January 9, 2007
    Publication date: July 10, 2008
    Inventors: KERRY BERNSTEIN, Paul William Coteus, Ibrahim (Abe) M. Elfadel, Philip George Emma, Kathryn W. Guarini, Thomas Fleischman, Allan Mark Hartstein, Ruchir Puri, Mark B. Ritter, Jeannine Madelyn Trewhella, Albert M. Young
  • Determining relative amount of usage of data retaining device based on potential of charge storing device
    Patent number: 7397718
    Abstract: A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: July 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Kenneth J. Goodnow, Clarence R. Ogilvie, Sebastian T. Ventrone, Keith R. Williams
  • DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE
    Publication number: 20080151672
    Abstract: A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.
    Type: Application
    Filed: March 11, 2008
    Publication date: June 26, 2008
    Inventors: Kerry Bernstein, Kenneth J. Goodnow, Clarence R. Ogilvie, Sebastian T. Ventrone, Keith R. Williams
  • System and method for designing a low leakage monotonic CMOS logic circuit
    Patent number: 7389478
    Abstract: A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic stages having a predominantly high input state or having a predominantly low input state; wherein the logic stages having the predominantly high input state, comprise one or more thin gate dielectric and high threshold voltage PFETs with respect to a reference PFET and one or more thick gate dielectric and low threshold voltage NFETs with respect to a reference NFET; and wherein the logic stages having the predominantly low input state, comprise one or more thick gate dielectric and low threshold voltage PFETs with respect to the reference PFET and one or more thin gate dielectric and high threshold voltage NFETs with respect to the reference NFET.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: June 17, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Norman J. Rohrer
  • DUAL WIRED INTEGRATED CIRCUIT CHIPS
    Publication number: 20080128812
    Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.
    Type: Application
    Filed: February 12, 2008
    Publication date: June 5, 2008
    Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
  • Dual wired integrated circuit chips
    Patent number: 7381627
    Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: June 3, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
  • FinFET transistor and circuit
    Patent number: 7368355
    Abstract: A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: May 6, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Edward J. Nowak, BethAnn Rainey
  • FinFET TRANSISTOR AND CIRCUIT
    Publication number: 20080099795
    Abstract: A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.
    Type: Application
    Filed: January 4, 2008
    Publication date: May 1, 2008
    Inventors: Kerry Bernstein, Edward Nowak, BethAnn Rainey
  • Wafer Level I/O Test, Repair and/or Customization Enabled by I/O layer
    Publication number: 20080068039
    Abstract: A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
    Type: Application
    Filed: November 27, 2007
    Publication date: March 20, 2008
    Inventors: Kerry Bernstein, Paul Coteus, Ibrahim Elfadel, Philip Emma, Daniel Friedman, Ruchir Puri, Mark Ritter, Jeannine Trewhella, Albert Young
  • ERROR CORRECTING LOGIC SYSTEM
    Publication number: 20080048711
    Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.
    Type: Application
    Filed: October 29, 2007
    Publication date: February 28, 2008
    Inventors: Kerry Bernstein, Philip Emma, John Fifield, Paul Kartschoke, William Klaasen, Norman Rohrer
  • Error correcting logic system
    Patent number: 7336102
    Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: February 26, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Philip G. Emma, John A. Fifield, Paul D. Kartschoke, William A. Klaasen, Norman J. Rohrer
  • METHOD AND ARCHITECTURE FOR POWER MANAGEMENT OF AN ELECTRONIC DEVICE
    Publication number: 20080024197
    Abstract: A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more switches.
    Type: Application
    Filed: August 29, 2007
    Publication date: January 31, 2008
    Inventors: Kerry Bernstein, Kenneth Goodnow, Clarence Ogilvie, Keith Williams, Sebastian Ventrone
  • Three-dimensional cascaded power distribution in a semiconductor device
    Publication number: 20080023731
    Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Applicant: International Business Machines Corporation
    Inventors: Kerry Bernstein, Paul W. Coteus, Philip George Emma, Allan Mark Hartstein, Stephen V. Kosonocky, Ruchir Puri, Mark B. Ritter
  • Intralevel decoupling capacitor, method of manufacture and testing circuit of the same
    Patent number: 7323382
    Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: January 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, John A. Bracchitta, William J. Cote, Tak H. Ning, Wilbur D. Pricer