Abstract: A display device includes a substrate, a semiconductor layer disposed on the substrate, and including a first channel portion, a second channel portion, a connecting portion disposed between the first channel portion and the second channel portion, and electrode regions, a first insulating layer disposed on the semiconductor layer, a gate conductor disposed on the first insulating layer and including a first gate electrode overlapping the first channel portion and a second gate electrode overlapping the second channel portion, signal lines disposed on the substrate, a first electrode electrically connected to at least one of electrode regions of the semiconductor layer, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer, and the first channel portion and the second channel portion of the semiconductor layer each have a first width greater than a second width of the connecting portion.

Abstract: The present invention relates to a composition for preventing or treating transplantation rejection or a transplantation rejection disease, comprising a novel compound and a calcineurin inhibitor. A co-administration of the present invention 1) reduces the activity of pathogenic Th1 cells or Th17 cells, 2) increases the activity of Treg cells, 3) has an inhibitory effect against side effects, such as tissue damage, occurring in the sole administration thereof, 4) inhibits various pathogenic pathways, 5) inhibits the cell death of inflammatory cells, and 6) increases the activity of mitochondria, in an in vivo or in vitro allogenic model, a transplantation rejection disease model, a skin transplantation model, and a liver-transplanted patient, and thus inhibits transplantation rejection along with mitigating side effects possibly occurring in the administration of a conventional immunosuppressant alone.

Abstract: An encoding/decoding apparatus and method for controlling a channel signal is disclosed, wherein the encoding apparatus may include an encoder to encode an object signal, a channel signal, and rendering information for the channel signal, and a bit stream generator to generate, as a bit stream, the encoded object signal, the encoded channel signal, and the encoded rendering information for the channel signal.

Abstract: A printed circuit board includes a first insulating layer, a plurality of first and second pads disposed on the first insulating layer, and a solder resist layer disposed on the first insulating layer, the solder resist layer having a plurality of first and second openings respectively exposing at least portions of the plurality of first and second pads. The first pad has a closed region having a side surface covered by the solder resist layer, and an open region having a side surface exposed by the first opening. The second pad has only a closed region having a side surface covered by the solder resist layer.

Abstract: A light emitting display device includes: a light emitting element; a second transistor connected to a scan line; a first transistor which applies a current to the light emitting element; a capacitor connected to a gate electrode of the first transistor; and a third transistor connected to an output electrode of the first transistor and the gate electrode of the first transistor. Channels of the second transistor, the first transistor, and the third transistor are disposed in a polycrystalline semiconductor layer, and a width of a channel of the third transistor is in a range of about 1 ?m to about 2 ?m, and a length of the channel of the third transistor is in a range of about 1 ?m to about 2.5 ?m.

Abstract: An apparatus for manufacturing an organic material includes an outer tube including an internal accommodating space, and at least one loading inner tube and at least one collecting inner tube disposed in the accommodation space, the loading inner tube including a mesh boat disposed in a first direction in which the loading inner tube extends.

Abstract: A substrate processing apparatus includes: a conveyor belt configured to have an outer surface on which a bottom surface of a substrate is seated; and a polishing head unit configured to face an upper surface of the substrate, wherein the polishing head unit includes: a polishing head connected to a driver; a polishing pad configured to face the polishing head; a polishing pad fixing ring disposed between the polishing head and the polishing pad; and a temperature sensor configured to overlap the polishing pad fixing ring and to be spaced apart from the polishing pad fixing ring.

Abstract: A memory device according to an embodiment of the present disclosure may include a string including a plurality of memory cells and a select transistor connected between a conductive line and the plurality of memory cells; a peripheral circuit configured to perform an erase operation of the string; and a control logic configured to control the peripheral circuit to increase a voltage level of an erase voltage applied to the conductive line for a first time period from time one to later time two at a first voltage-time slope, and increase the voltage level of the erase voltage for a second time period from time two to later time three at a second voltage-time slope, during the erase operation, wherein the second voltage-time slope is greater than the first voltage-time slope.

Abstract: A memory controller having an improved operation speed controls a memory device including a plurality of memory blocks. The memory controller includes: a remaining count determiner configured to determine a remaining count that is a number of program and erase operations to be additionally performed in the memory device based on a program/erase count received from the memory device, a retention period calculator configured to determine a retention period based on a power-off time and a power-on time of the memory device and a read voltage determiner configured to generate a changed read voltage table based on a default read voltage table and a coefficient determined according to the remaining count, and determine a read voltage to be used in the memory device according to the retention period among read voltages included in the changed read voltage table.

Abstract: A substrate processing apparatus includes: a conveyor belt configured to have an outer surface on which a bottom surface of a substrate is seated; and a polishing head unit configured to face an upper surface of the substrate, wherein the polishing head unit includes: a polishing head connected to a driver; a polishing pad configured to face the polishing head; a polishing pad fixing ring disposed between the polishing head and the polishing pad; and a temperature sensor configured to overlap the polishing pad fixing ring and to be spaced apart from the polishing pad fixing ring.

Abstract: A method, system, and quiz server for providing a quiz and an advertisement simultaneously in an IMS chat is provided. The method includes creating a chat room from a mobile terminal while inviting a pre-registered quizbot as a chat participant, displaying a quiz and an advertisement within the chat room on the mobile terminal in the form of a chat message composed by the quizbot, and displaying, within the chat room, an answer of a certain chat participant with respect to the quiz, and inputting a result of determination of whether the answer is correct into the chat room by using the quizbot, displaying, within the chat room, the answer of the certain chat participant with respect to the quiz, and inputting a result of determination of whether the answer is correct into the chat room by using the quizbot.

Abstract: A memory system includes: a memory device; and a non-erase block management device suitable for determining, when an erase operation is performed on a first memory block included in the memory device, whether to perform a read operation on a second word line of a second memory block, according to a location of a first word line, which is a target word line for a read operation on the second memory block, wherein the second word line includes a target word line for a dummy read operation.

Abstract: A controller, for use in memory system, includes: a processor configured to control a read operation for a target memory area of a memory device in response to a read command received from a host; and an error correction circuit configured to perform an error correction operation on read data corresponding to the read operation, wherein the processor selects an optimum read voltage set among a plurality of read voltage sets in a read retry table, based on an erase write cycling (EW) number of the target memory area and a fail bit number of the read data.

Abstract: A memory controller having an improved operation speed controls a memory device including a plurality of memory blocks. The memory controller includes: a remaining count determiner configured to determine a remaining count that is a number of program and erase operations to be additionally performed in the memory device based on a program/erase count received from the memory device, a retention period calculator configured to determine a retention period based on a power-off time and a power-on time of the memory device and a read voltage determiner configured to generate a changed read voltage table based on a default read voltage table and a coefficient determined according to the remaining count, and determine a read voltage to be used in the memory device according to the retention period among read voltages included in the changed read voltage table.

Abstract: A method, system, and quiz server for providing a quiz and an advertisement simultaneously in an IMS chat is provided. The method includes creating a chat room from a mobile terminal while inviting a pre-registered quizbot as a chat participant, displaying a quiz and an advertisement within the chat room on the mobile terminal in the form of a chat message composed by the quizbot, and displaying, within the chat room, an answer of a certain chat participant with respect to the quiz, and inputting a result of determination of whether the answer is correct into the chat room by using the quizbot, displaying, within the chat room, the answer of the certain chat participant with respect to the quiz, and inputting a result of determination of whether the answer is correct into the chat room by using the quizbot.

Abstract: A memory system includes: a memory device; and a non-erase block management device suitable for determining, when an erase operation is performed on a first memory block included in the memory device, whether to perform a read operation on a second word line of a second memory block, according to a location of a first word line, which is a target word line for a read operation on the second memory block, wherein the second word line includes a target word line for a dummy read operation.

Abstract: A controller which controls an operation of a semiconductor memory device including a plurality of memory blocks. The controller includes a randomizer. The randomizer generates randomized data, based on a block address of a target memory block, and a program-erase count value or the target memory block. Accordingly, the performance of a memory system is improved.

Abstract: A memory device may include: a memory cell array comprising a plurality of search regions, each of the search regions comprising a plurality of group regions, each of the group regions comprising a flag cell, each flag cell comprising information indicating whether the corresponding group region is programmed; a voltage generator suitable for generating a read bias voltage for the memory cell array according to a voltage control signal; and a memory controller suitable for selecting a search region and controlling the voltage generator to adjust the read bias voltage based on information of flag cell of the selected search region when a read command is received, and controlling a read operation for the selected search region based on the adjusted read bias voltage.

Abstract: An operating method of a data storage device includes setting a first page access unit using a first page electrically coupled with a first word line of a first plane and a second page electrically coupled with a second word line of a second plane; and setting a second page access unit using a third page electrically coupled with a second word line of the first plane and a fourth page electrically coupled with a first word line of the second plane.

Abstract: A memory device may include: a memory cell array comprising a plurality of search regions, each of the search regions comprising a plurality of group regions, each of the group regions comprising a flag cell, each flag cell comprising information indicating whether the corresponding group region is programmed; a voltage generator suitable for generating a read bias voltage for the memory cell array according to a voltage control signal; and a memory controller suitable for selecting a search region and controlling the voltage generator to adjust the read bias voltage based on information of flag cell of the selected search region when a read command is received, and controlling a read operation for the selected search region based on the adjusted read bias voltage.