Abstract: Techniques are disclosed for forming a through-body-via (TBV) in a semiconductor die. In accordance with some embodiments, a TBV provided using the disclosed techniques includes a polymer-based barrier layer and an electrically conductive seed layer formed by applying an electrically conductive ink directly to the barrier layer and then curing it in situ. In some embodiments, after curing, the resultant seed layer may be a thin, substantially conformal, electrically conductive metal film over which the TBV interconnect metal can be deposited. In some example cases, a polyimide, parylene, benzocyclobutene (BCB), and/or polypropylene carbonate (PPC) barrier layer and an ink containing copper (Cu) and/or silver (Ag), of nanoparticle-based or metal complex-based formulation, may be used in forming the TBV.

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, the IC die may include a semiconductor substrate, a plurality of active components disposed on a first side of the semiconductor substrate, and a plurality of passive components disposed on a second side of the semiconductor substrate. In embodiments the second side may be disposed opposite the first side. The passive components may, in some embodiments, include capacitors and/or resistors while the active components may, in some embodiments, include transistors. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe a die with integrated microphone device using through-silicon vias (TSVs) and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a semiconductor substrate having a first side and a second side disposed opposite to the first side, an interconnect layer formed on the first side of the semiconductor substrate, a through-silicon via (TSV) formed through the semiconductor substrate and configured to route electrical signals between the first side of the semiconductor substrate and the second side of the semiconductor substrate, and a microphone device formed on the second side of the semiconductor substrate and electrically coupled with the TSV. Other embodiments may be described and/or claimed.

Abstract: An embodiment includes a semiconductor apparatus comprising: a redistribution layer (RDL) including a patterned RDL line having two RDL sidewalls, the RDL comprising a material selected from the group comprising Cu and Au; protective sidewalls directly contacting the two RDL sidewalls; a seed layer including the material; and a barrier layer; wherein (a) the RDL line has a RDL line width orthogonal to and extending between the two RDL sidewalls, and (b) the seed and barrier layers each include a width parallel to and wider than the RDL line width. Other embodiments are described herein.

Abstract: A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

Abstract: Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).

Abstract: Techniques are disclosed for forming a through-body-via (TBV) in a semiconductor die. In accordance with some embodiments, a TBV provided using the disclosed techniques includes a polymer-based barrier layer and an electrically conductive seed layer formed by applying an electrically conductive ink directly to the barrier layer and then curing it in situ. In some embodiments, after curing, the resultant seed layer may be a thin, substantially conformal, electrically conductive metal film over which the TBV interconnect metal can be deposited. In some example cases, a polyimide, parylene, benzocyclobutene (BCB), and/or polypropylene carbonate (PPC) barrier layer and an ink containing copper (Cu) and/or silver (Ag), of nanoparticle-based or metal complex-based formulation, may be used in forming the TBV.

Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.

Abstract: A method and apparatus for masking and unmasking content. A system configured to practice the example method embodiment parses a markup language document to identify a location of a section of the markup language document to mask and selects, based on a content type for content within the section, replacement content for the section. Then the system saves a copy of the section in a storage external to the markup language document. The system inserts the replacement content in the markup language document at the location in place of the section to mask the section while preserving formatting and layout of the markup language document. Upon receiving an indication to restore the section, the system inserts the copy of the section in the markup language document at the location in place of the replacement content.

Abstract: A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

Abstract: An embodiment includes a semiconductor apparatus comprising: a redistribution layer (RDL) including a patterned RDL line having two RDL sidewalls, the RDL comprising a material selected from the group comprising Cu and Au; protective sidewalls directly contacting the two RDL sidewalls; a seed layer including the material; and a barrier layer; wherein (a) the RDL line has a RDL line width orthogonal to and extending between the two RDL sidewalls, and (b) the seed and barrier layers each include a width parallel to and wider than the RDL line width. Other embodiments are described herein.

Abstract: A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

Abstract: A structure and method of handling a device wafer during through-silicon via (TSV) processing are described in which a device wafer is bonded to a temporary support substrate with a permanent thermosetting material. Upon removal of the temporary support substrate a planar frontside bonding surface including a reflowed solder bump and the permanent thermosetting material is exposed.

Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.

Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.

Abstract: A structure and method of handling a device wafer during through-silicon via (TSV) processing are described in which a device wafer is bonded to a temporary support substrate with a permanent thermosetting material. Upon removal of the temporary support substrate a planar frontside bonding surface including a reflowed solder bump and the permanent thermosetting material is exposed.

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.

Abstract: Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In one embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed.