Patents by Inventor Kevin J. Lee

Kevin J. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080054416
    Abstract: Embodiments of buffer coatings for semiconductor and integrated circuit manufacturing are presented herein.
    Type: Application
    Filed: September 6, 2006
    Publication date: March 6, 2008
    Inventors: Michael D. Goodner, Kevin J. Lee
  • Publication number: 20080032418
    Abstract: The invention relates to an assay for determining if ligands bind to a receptor. The method involves the use of complexes, where the receptor is linked to a reporter molecule via an (His)n chain. When ligand binds to the receptor, the reporter molecule, which is preferably a peryline, yields a signal.
    Type: Application
    Filed: February 9, 2004
    Publication date: February 7, 2008
    Inventors: David Adams, Kevin J. Lee
  • Publication number: 20080026318
    Abstract: A composite photoresist comprises a photoresist material and a filler material dispersed within the photoresist material, wherein the filler material includes a plurality of nanoparticles. The photoresist material may comprise an acrylic-based photoresist, a novolak-based photoresist, a polyhydroxystyrene-based photoresist, a SLAM, or a BARC. The filler material may comprise base-soluble styrene-butadiene rubber nanospheres, nitrile-butadiene rubber nanospheres, polystyrene-based nanoparticles, acrylic-based nanoparticles, or inorganic nanoparticles. The nanoparticles may have an average diameter that is between around 10 nm and around 1000 nm and may have a loading in the photoresist material that is between around 5% and 50%. The composite photoresist may be used to form die-side metal bumps for use in a C4 connection that have a roughened sidewall surface but a smooth top surface.
    Type: Application
    Filed: July 27, 2006
    Publication date: January 31, 2008
    Inventors: Kurt Schultz, Kevin J. Lee, Michael D. Goodner, Shane Nolen
  • Publication number: 20080003715
    Abstract: Embodiments of the invention include apparatuses and methods relating to die-side bumps having a tapered cross-section. In one embodiment, the tapered die-side bump is electrically coupled to a solder bump on a package substrate.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Kevin J. Lee, Figen T. Akin, Kurt Schultz, Raman Vaidyanathan, Shane A. Nolen, Adwait Telang
  • Patent number: 7238798
    Abstract: The present invention relates to insect odorant receptor genes and methods for identifying odorant receptor genes. The invention provides nucleotide sequences of insect odorant receptor genes Or83b, amino acid sequences of their encoded proteins (including peptides or polypeptides), and related products and methods. The nucleic acids of the invention may be operatively linked to promoter sequences and transformed into host cells. Methods of production of an Or83b odorant receptor protein (e.g., by recombinant means), and derivatives and analogs thereof, are provided. Antibodies to an Or83b odorant receptor protein, and derivatives and analogs thereof, are provided. Methods for identifying molecules that bind or modulate the activity of these Or83b odorant receptor genes are provided. Molecules found to bind or modulate the activity of Or83b genes may be formulated into pest control agents by providing a carrier.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: July 3, 2007
    Assignee: SentiSearch, Inc.
    Inventors: Kevin J. Lee, Thuy-Ai T. Nguyen, Brian Kloss
  • Patent number: 7088005
    Abstract: The present invention includes a method that provides a first wafer; forms a first raised contact from a first plug on the first wafer; provides a second wafer; forms a second raised contact from a second plug on the second wafer; applies an anisotropic conductive adhesive over the first wafer; aligns the second wafer to the first wafer; attaches the second wafer to the anisotropic conductive adhesive to form a continuous and conductive path between the first raised contact and the second raised contact. The present invention also includes a structure that has an anisotropic conductive film, the anisotropic conductive film has a front surface and a rear surface; a first raised contact is located over the front surface, the first raised contact forming part of a first wafer; and a second raised contact located over the rear surface, the second raised contact forming part of a second wafer, where the second raised contact faces the first raised contact.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventor: Kevin J. Lee
  • Patent number: 7064446
    Abstract: Apparatus and methods of fabricating an under bump metallization structure including an adhesion layer abutting a conductive pad, a molybdenum-containing barrier layer abutting the adhesion layer, a wetting layer abutting the molybdenum-containing barrier layer, and high tin content solder material abutting the wetting layer. The wetting layer may be substantially subsumed in the high content solder forming an intermetallic compound layer. The molybdenum-containing barrier layer prevents the movement of tin in the high tin content solder material from migrating to dielectric layers abutting the conductive pad and potentially causing delamination and/or attacking any underlying structures, particularly copper structures, which may be present.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: June 20, 2006
    Assignee: Intel Corporation
    Inventors: John P. Barnak, Gerald B. Feldewerth, Ming Fang, Kevin J. Lee, Tzuen-Luh Huang, Harry Y. Liang, Seshu V. Sattiraju, Margherita Chang, Andrew W. H. Yeoh
  • Patent number: 7049076
    Abstract: The invention relates to a method for determining if a test compound, or a mix of compounds, modulates the interaction between two proteins of interest. The determination is made possible via the use of two recombinant molecules, one of which contains the first protein a cleavage site for a proteolytic molecules, and an activator of a gene. The second recombinant molecule includes the second protein and the proteolytic molecule. If the test compound binds to the first protein, a reaction is initiated whereby the activator is cleaved, and activates a reporter gene.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: May 23, 2006
    Assignees: Sentigen Biosciences, Inc., The Trustees of Columbia University of the City of New York
    Inventors: Kevin J. Lee, Richard Axel, Walter Strapps, Gilad Barnea
  • Patent number: 6984302
    Abstract: The invention discloses a method of electroplating a material onto a semiconductor substrate. A substrate is placed in a cylindrical processing chamber enclosure. A nozzle for spraying a liquid electroplating solution opposes the top surface of the substrate. The electroplating solution flows through the nozzle and outward angularly from the tip of the nozzle, so that the solution flows rotationally on the surface of the substrate.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: January 10, 2006
    Assignee: Intel Corporation
    Inventor: Kevin J. Lee
  • Patent number: 6943440
    Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric with spray coating or lamination over a surface with high aspect ratio structures.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: September 13, 2005
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, Kevin J. Lee, Anna M. George, Steven Towle
  • Publication number: 20040178059
    Abstract: A process for selectively removing a conductive layer from a wafer that includes sub-micron sized noble metal interconnect features is disclosed, the method including placing the wafer into an electrolyte solution. Also immersed in the electrolyte solution are a counter electrode, a reference electrode, and a working electrode. The wafer is coupled to the working electrode terminal on a potentiostat. The counter electrode is connected to the counter electrode terminal on a potentiostat, and the reference electrode is connected to a reference electrode terminal on the potentiostat. The potentiostat adjusts the electrical current flowing between the wafer and the counter electrode to maintain a constant voltage between the wafer and the reference electrode as the conductive layer is removed. The removal of the conductive layer is finished when the current that maintains the constant voltage between the wafer and the reference electrode drops to a residual level.
    Type: Application
    Filed: March 24, 2004
    Publication date: September 16, 2004
    Inventor: Kevin J. Lee
  • Publication number: 20040094507
    Abstract: A cross-linked photoresist may be stripped without using water to reduce substrate corrosion. In one embodiment, a transesterification reaction may use an alcohol instead of water as the co-solvent for an organic base.
    Type: Application
    Filed: November 14, 2002
    Publication date: May 20, 2004
    Inventors: Michael D. Goodner, Kevin J. Lee, Robert P. Meagley
  • Patent number: 6737360
    Abstract: A process for selectively removing a conductive layer from a wafer that includes sub-micron sized noble metal interconnect features is disclosed. The wafer having sub-micron sized noble metal interconnect features and a conductive film to be removed is placed into an electrolyte solution. Also immersed in the electrolyte solution are a counter electrode, a reference electrode, and a working electrode. The wafer is coupled to the working electrode terminal on a potentiostat. The counter electrode is connected to the counter electrode terminal on a potentiostat, and the reference electrode is connected to a reference electrode terminal on the potentiostat. The potentiostat adjusts the electrical current flowing between the wafer and the counter electrode to maintain a constant voltage between the wafer and the reference electrode as the conductive layer is removed.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: May 18, 2004
    Assignee: Intel Corporation
    Inventor: Kevin J. Lee
  • Publication number: 20020119671
    Abstract: A process for selectively removing a conductive layer from a wafer that includes sub-micron sized noble metal interconnect features is disclosed. The wafer having sub-micron sized noble metal interconnect features and a conductive film to be removed is placed into an electrolyte solution. Also immersed in the electrolyte solution are a counter electrode, a reference electrode, and a working electrode. The wafer is coupled to the working electrode terminal on a potentiostat. The counter electrode is connected to the counter electrode terminal on a potentiostat, and the reference electrode is connected to a reference electrode terminal on the potentiostat. The potentiostat adjusts the electrical current flowing between the wafer and the counter electrode to maintain a constant voltage between the wafer and the reference electrode as the conductive layer is removed.
    Type: Application
    Filed: December 30, 1999
    Publication date: August 29, 2002
    Inventor: KEVIN J. LEE
  • Patent number: 6384481
    Abstract: A single step electroplating process for interconnect via fill and metal line formation on a semiconductor substrate is disclosed. In this process, a barrier layer is formed onto a surface of a substrate that has at least one via and then a conductive layer is formed onto the barrier layer. Next, a photoresist layer is applied and patterned on top of the conductive layer. The via plugs and metal lines are then deposited on the substrate simultaneously using an electroplating process. After the electroplating process is completed, the photoresist and the conductive layer between the deposited metal lines are removed. The process provides a simple, economical and highly controllable means of forming metal interconnect systems while avoiding the difficulties associated with depositing and patterning metal by traditional semiconductor fabrication techniques.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: May 7, 2002
    Assignee: Intel Corporation
    Inventors: Makarem Hussein, Kevin J. Lee, Sam Sivakumar
  • Patent number: 6346144
    Abstract: One embodiment of the present invention includes a chemical-mechanical polishing (CMP) slurry. The slurry is comprised of one or more ferrocenium salts that is or are reduced, during use, to ferrocene. The slurry also includes an abrasive and a concentration of hydronium ions effective to impart a pH of less than 7.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: February 12, 2002
    Assignee: Intel Corporation
    Inventor: Kevin J. Lee
  • Publication number: 20020000383
    Abstract: The invention discloses a method of electroplating a material onto a semiconductor substrate. A substrate is placed in a cylindrical processing chamber enclosure. A nozzle for spraying a liquid electroplating solution opposes the top surface of the substrate. The electroplating solution flows through the nozzle and outward angularly from the tip of the nozzle, so that the solution flows rotationally on the surface of the substrate.
    Type: Application
    Filed: December 30, 1998
    Publication date: January 3, 2002
    Inventor: KEVIN J. LEE
  • Patent number: 6214098
    Abstract: One embodiment of the present invention includes a chemical-mechanical polishing (CMP) slurry. The slurry is comprised of one or more ferrocenium salts that is or are reduced, during use, to ferrocene. The slurry also includes an abrasive and a concentration of hydronium ions effective to impart a pH of less than 7.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: April 10, 2001
    Assignee: Intel Corporation
    Inventor: Kevin J. Lee
  • Patent number: 6077337
    Abstract: One embodiment of the present invention includes a chemical-mechanical polishing (CMP) slurry. The slurry is comprised of one or more ferrocenium salts that is or are reduced, during use, to ferrocene. The slurry also includes an abrasive and a concentration of hydronium ions effective to impart a pH of less than 7.
    Type: Grant
    Filed: December 1, 1998
    Date of Patent: June 20, 2000
    Assignee: Intel Corporation
    Inventor: Kevin J. Lee
  • Patent number: 6020266
    Abstract: A single step electroplating process for interconnect via fill and metal line formation on a semiconductor substrate is disclosed. In this process, a barrier layer is formed onto a surface of a substrate that has at least one via and then a conductive layer is formed onto the barrier layer. Next, a photoresist layer is applied and patterned on top of the conductive layer. The via plugs and metal lines are then deposited on the substrate simultaneously using an electroplating process. After the electroplating process is completed, the photoresist and the conductive layer between the deposited metal lines are removed. The process provides a simple, economical and highly controllable means of forming metal interconnect systems while avoiding the difficulties associated with depositing and patterning metal by traditional semiconductor fabrication techniques.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: February 1, 2000
    Assignee: Intel Corporation
    Inventors: Makarem Hussein, Kevin J. Lee, Sam Sivakumar