Abstract: The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.

Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.

Abstract: The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.

Abstract: The present disclosure describes apparatus and methods for processing microfeature workpieces, e.g., by depositing material on a microelectronic semiconductor using atomic layer deposition. Some of these apparatus include microfeature workpiece holders that include gas distributors. One exemplary implementation provides a microfeature workpiece holder adapted to hold a plurality of microfeature workpieces. This workpiece holder includes a plurality of workpiece supports and a gas distributor. The workpiece supports are adapted to support a plurality of microfeature workpieces in a spaced-apart relationship to define a process space adjacent a surface of each microfeature workpiece. The gas distributor includes an inlet and a plurality of outlets, with each of the outlets positioned to direct a flow of process gas into one of the process spaces.

Abstract: A method of forming a capacitor includes forming first capacitor electrode material over a semiconductor substrate. A silicon nitride comprising layer is formed over the first capacitor electrode material. The semiconductor substrate with silicon nitride comprising layer is provided within a chamber. An oxygen comprising plasma is generated remote from the chamber. The remote plasma generated oxygen is fed to the semiconductor substrate within the chamber at a substrate temperature of no greater than 750° C. effective to form a silicon oxide comprising layer over the silicon nitride comprising layer. After the feeding, a second capacitor electrode material is formed over the silicon oxide comprising layer. Methods of forming capacitor dielectric layers are also disclosed.

Abstract: The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.

Abstract: Insulating material is deposited onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of: A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and B. Depositing by sputtering the insulating material onto the open surface of the gate dielectric separating the two wordline stacks.

Abstract: A method of adjusting the threshold voltage of semiconductor devices by incorporating nitride into the isolation layer so as to decrease the mobility of charge carriers and thereby increase the threshold voltage required to activate the device. The nitrogen incorporation method may comprise of decoupled plasma nitridization (DPN) and the DPN can be performed in-situ during gate oxide formation. The amount of threshold voltage can be varied by adjusting the DPN treatment time and processing parameters.

Abstract: A method of forming a capacitor includes forming first capacitor electrode material over a semiconductor substrate. A silicon nitride comprising layer is formed over the first capacitor electrode material. The semiconductor substrate with silicon nitride comprising layer is provided within a chamber. An oxygen comprising plasma is generated remote from the chamber. The remote plasma generated oxygen is fed to the semiconductor substrate within the chamber at a substrate temperature of no greater than 750° C. effective to form a silicon oxide comprising layer over the silicon nitride comprising layer. After the feeding, a second capacitor electrode material is formed over the silicon oxide comprising layer. Methods of forming capacitor dielectric layers are also disclosed.

Abstract: The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 Å above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer. The invention encompasses a method of forming a pair of transistors associated with a semiconductor substrate. First and second regions of the substrate are defined. A first oxide region is formed to cover the first region of the substrate, and to not cover the second region of the substrate. Nitrogen is formed within the first oxide region, and a first conductive layer is formed over the first oxide region. After the first conductive layer is formed, a second oxide region is formed over the second region of the substrate.

Abstract: A partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and suppressed floating body effect is disclosed, as well as a simple method for its fabrication. A thin Si/Ge epitaxial layer is grown between two adjacent epitaxial silicon layers of a SOI substrate, and as part of the silicon epitaxial growth. The thin Si/Ge epitaxial layer introduces misfit dislocations at the interface between the thin Si/Ge epitaxial layer and the adjacent epitaxial silicon layers, which removes undesired charge build up within the substrate.

Abstract: The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate including a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which includes a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further includes a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure comprises a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.

Abstract: A method of forming a capacitor includes forming first capacitor electrode material over a semiconductor substrate. A silicon nitride comprising layer is formed over the first capacitor electrode material. The semiconductor substrate with silicon nitride comprising layer is provided within a chamber. An oxygen comprising plasma is generated remote from the chamber. The remote plasma generated oxygen is fed to the semiconductor substrate within the chamber at a substrate temperature of no greater than 750° C. effective to form a silicon oxide comprising layer over the silicon nitride comprising layer. After the feeding, a second capacitor electrode material is formed over the silicon oxide comprising layer. Methods of forming capacitor dielectric layers are also disclosed.

Abstract: Insulating material is deposited onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of:

Abstract: The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate containing a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which has a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further contains a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.

Abstract: The invention encompasses semiconductor assemblies that include a semiconductor substrate having a first region and a second region defined therein. A first oxide region is on the substrate and covers the first region of the substrate. The first oxide region has nitrogen provided therein and substantially all of the nitrogen is at least 10 Å above the semiconductor substrate. A first conductive layer is over the first oxide region and defines a first transistor gate. First source/drain regions are proximate the first transistor gate and gatedly connected to one another by the first transistor gate. The second region is covered by a second oxide region. A second conductive layer is over the second oxide region and defines a second transistor gate. Second source/drain regions are proximate the second transistor gate and gatedly connected to one another by the second transistor gate.

Abstract: The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 Å above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.

Abstract: The invention includes a method of forming a programmable memory device. A tunnel oxide is formed to be supported by a semiconductor substrate. A stack is formed over the tunnel oxide. The stack comprises a floating gate, dielectric mass and control gate. The stack has a top, and has opposing sidewalls extending downwardly from the top. The dielectric mass includes silicon nitride. Silicon nitride spacers are formed along sidewalls of the stack, and a silicon nitride cap is formed over a top of the stack. The silicon nitride within the dielectric mass, cap and/or sidewall spacers is formed from trichlorosilane and ammonia.

Abstract: A partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and suppressed floating body effect is disclosed, as well as a simple method for its fabrication. A thin Si/Ge epitaxial layer is grown between two adjacent epitaxial silicon layers of a SOI substrate, and as part of the silicon epitaxial growth. The thin Si/Ge epitaxial layer introduces misfit dislocations at the interface between the thin Si/Ge epitaxial layer and the adjacent epitaxial silicon layers, which removes undesired charge build up within the substrate.

Abstract: The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate having a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which has a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further includes a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.