Abstract: Insulating material is deposited onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of: A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and B. Depositing by sputtering the insulating material onto the open surface of the gate dielectric separating the two wordline stacks.

Abstract: The invention includes a method of forming a DRAM cell. A first substrate is formed to comprise first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate comprising a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which comprises a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further comprises a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure comprises a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.

Abstract: Methods of forming FLASH field effect transistor gates and a non-FLASH field effect transistor gates are described. In one implementation, a substrate comprising first and second semiconductive material portions is provided. A FLASH transistor gate is partially formed to include at least a first gate dielectric material received over the first semiconductive material portion, a floating gate material overlying the first gate dielectric material, and a second gate dielectric material received over the floating gate material. The second gate dielectric material comprises silicon nitride. In a common oxidizing step, the silicon nitride of the second gate dielectric material and the second semiconductive material portion are oxidized effective to form both a) a gate oxide layer of a non-FLASH transistor gate overlying the second semiconductive material portion, and b) silicon dioxide as part of the second gate dielectric material of the FLASH transistor gate. Additional implementations are contemplated.

Abstract: Methods of forming FLASH field effect transistor gates and a non-FLASH field effect transistor gates are described. In one implementation, a substrate comprising first and second semiconductive material portions is provided. A FLASH transistor gate is partially formed to include at least a first gate dielectric material received over the first semiconductive material portion, a floating gate material overlying the first gate dielectric material, and a second gate dielectric material received over the floating gate material. The second gate dielectric material comprises silicon nitride. In a common oxidizing step, the silicon nitride of the second gate dielectric material and the second semiconductive material portion are oxidized effective to form both a) a gate oxide layer of a non-FLASH transistor gate overlying the second semiconductive material portion, and b) silicon dioxide as part of the second gate dielectric material of the FLASH transistor gate. Additional implementations are contemplated.

Abstract: A method of forming a capacitor includes forming first capacitor electrode material over a semiconductor substrate. A silicon nitride comprising layer is formed over the first capacitor electrode material. The semiconductor substrate with silicon nitride comprising layer is provided within a chamber. An oxygen comprising plasma is generated remote from the chamber. The remote plasma generated oxygen is fed to the semiconductor substrate within the chamber at a substrate temperature of no greater than 750° C. effective to form a silicon oxide comprising layer over the silicon nitride comprising layer. After the feeding, a second capacitor electrode material is formed over the silicon oxide comprising layer. Methods of forming capacitor dielectric layers are also disclosed.

Abstract: The invention includes a method of forming a DRAM cell. A first substrate is formed to comprise first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate comprising a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM substructures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which comprises a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further comprises a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure comprises a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.

Abstract: Insulating material is deposited onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of: A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and B. Depositing by sputtering the insulating material onto the open surface of the gate dielectric separating the two wordline stacks.

Abstract: A partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and suppressed floating body effect is disclosed, as well as a simple method for its fabrication. A thin Si/Ge epitaxial layer is grown between two adjacent epitaxial silicon layers of a SOI substrate, and as part of the silicon epitaxial growth. The thin Si/Ge epitaxial layer introduces misfit dislocations at the interface between the thin Si/Ge epitaxial layer and the adjacent epitaxial silicon layers, which removes undesired charge build up within the substrate.

Abstract: The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate including a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which includes a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further includes a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.

Abstract: Insulating material is deposited onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of:

Abstract: The present invention provides a flash memory cell utilizing an ambient containing atomic oxidation for fabrication of a second or top oxide layer in a oxide-nitride-oxide insulating structure. The second or top oxide layer is grown utilizing atomic oxygen containing ambients. A silicon nitride is thus oxidized substantially faster than standard steam or oxygen ambients.

Abstract: The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 Å above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer. The invention encompasses a method of forming a pair of transistors associated with a semiconductor substrate. First and second regions of the substrate are defined. A first oxide region is formed to cover the first region of the substrate, and to not cover the second region of the substrate. Nitrogen is formed within the first oxide region, and a first conductive layer is formed over the first oxide region. After the first conductive layer is formed, a second oxide region is formed over the second region of the substrate.

Abstract: The invention includes a method of forming a DRAM cell. A first substrate is formed to comprise first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate comprising a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which comprises a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further comprises a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure comprises a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.

Abstract: A partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and suppressed floating body effect is disclosed, as well as a simple method for its fabrication. A thin Si/Ge epitaxial layer is grown between two adjacent epitaxial silicon layers of a SOI substrate, and as part of the silicon epitaxial growth. The thin Si/Ge epitaxial layer introduces misfit dislocations at the interface between the thin Si/Ge epitaxial layer and the adjacent epitaxial silicon layers, which removes undesired charge build up within the substrate.