Abstract: The present invention is directed to a sigma-delta digital to analog converted (DAC) including a digital-sigma delta modulator, a decimation filter, and a multi-bit DAC. The digital sigma-delta modulator receives a digital input signal and produces a quantized digital signal therefrom. The decimation filter receives the quantized digital signal and produces a decimated digital signal therefrom. The multi-bit DAC receives the decimated digital signal and produces an analog output signal therefrom. The analog output signal is representative of the digital input signal.

Abstract: Methods and apparatuses for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC). In an embodiment, a range signal is produced based on the digital input code. The range signal specifies which one of a plurality of ranges the digital input code is within. A density code is also produced, preferably, using a shuffling algorithm. The density code specifies a level within the range expressed by the range signal. The range signal and the density code are then combined to produce a plurality of sub-codes, a sum of the plurality of sub-codes equaling the digital input code.

Abstract: The present invention is directed to a sigma-delta digital to analog converted (DAC) including a digital-sigma delta modulator, a decimation filter, and a multi-bit DAC. The digital sigma-delta modulator receives a digital input signal and produces a quantized digital signal therefrom. The decimation filter receives the quantized digital signal and produces a decimated digital signal therefrom. The multi-bit DAC receives the decimated digital signal and produces an analog output signal therefrom. The analog output signal is representative of the digital input signal.

Abstract: A system for reducing the startup current demand of a computer system by providing clock signals at normal operating frequencies to a plurality of computer components in a staggered progression. The computer system includes a clock buffer having a plurality of outputs each for providing a clock signal to at least one computer component. During the startup of the computer system, the clock buffer provides at each output a clock signal at a normal operating frequency to each component in a staggered progression with the other outputs. Consequently, only one component (or component group) becomes operational at a time during the startup of the computer system. In one example, each output of the clock buffer is coupled to a memory module that includes multiple SDRAM chips.

Abstract: The present invention is directed to a sigma-delta digital to analog converted (DAC) including a digital-sigma delta modulator, a decimation filter, and a multi-bit DAC. The digital sigma-delta modulator receives a digital input signal and produces a quantized digital signal therefrom. The decimation filter receives the quantized digital signal and produces a decimated digital signal therefrom. The multi-bit DAC receives the decimated digital signal and produces an analog output signal therefrom. The analog output signal is representative of the digital input signal.

Abstract: Methods and apparatuses for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC). In an embodiment, a range signal is produced based on the digital input code. The range signal specifies which one of a plurality of ranges the digital input code is within. A density code is also produced, preferably, using a shuffling algorithm. The density code specifies a level within the range expressed by the range signal. The range signal and the density code are then combined to produce a plurality of sub-codes, a sum of the plurality of sub-codes equaling the digital input code.

Abstract: Methods and apparatuses for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC). In an embodiment, the multi-bit DAC is constructed from K separate multi-element sub-DACs, where K and the number of elements in each sub-DAC are each preferably greater than two. A received digital input code is split into a set of K sub-codes corresponding to the digital input code. The set of K sub-codes can have one of at least N different sub-code orders that specify an order of each of the K sub-codes with respect to one another, where N>2. A sum of the K sub-codes equals the digital input code. One of the at least N different sub-code orders is selected using a shuffling algorithm. Then, each sub-code in the set of K sub-codes is output in accordance with the selected sub-code order.

Abstract: A network gateway is configured to facilitate on line and off line bi-directional communication between a number of near end data and telephony devices with far end data termination devices via a hybrid fiber coaxial network and a cable modem termination system. The described network gateway combines a QAM receiver, a transmitter, a DOCSIS MAC, a CPU, a voice and audio processor, a voice synchronizer, an Ethernet MAC, and a USB controller to provide high performance and robust operation.

Abstract: An apparatus and method for automatically analyzing and controlling intensity of a train of high speed, high power multi-level optical pulses. The invention includes an optical pulse generator for generating the train of high speed, high power, multi-level optical pulses, wherein the optical pulse generator provides a low optical intensity level and a medium optical intensity level and a high optical intensity level. A photodetector is optically coupled with the optical pulse generator for generating a train of electrical pulses having amplitude levels in response to optical intensity levels of the train of optical pulses. At least one reference is employed, wherein an analyzer electrically coupled with the reference and the photodetector for analyzing the amplitude levels of the train of electrical pulses in comparison to the reference. A controller is electrically coupled with analyzer for generating a high correction signal based upon the analysis of the amplitude levels.

Abstract: A socket connector and a card-edge is provided for electrical busses. In one embodiment, a socket is provided for electrical busses that require each end of the bus to be terminated that does not require a termination card. In another embodiment, a socket connector is provided for electrical busses that flow through several aligned socket connectors. The design of the socket connector connects a bus to termination resistors located on a circuit board of the socket connector by cross-connecting the signal through the signal pins inside the socket connector.

Abstract: A system and method is provided for supplying power over a home phone line network in a manner that is interoperable with other voice and data services operating on the same network. The system includes a power source coupled to the home phone line network. The power source includes an AC signal generator that generates an AC signal at a selected frequency. The power source also includes a band pass filter for removing unwanted harmonics from the AC signal, thereby generating a filtered AC signal for powering one or more devices on the home phone line network. One or more devices attached to the home phone line network, such as a telephone adapter or telephone, receives the filtered AC signal. Each device comprises a second band pass filter and an AC/DC converter. The second band pass filter passes the filtered AC signal to the AC/DC converter and prevents the introduction of undesired harmonics onto the home phone line network from the AC/DC converter.

Abstract: A chassis detection circuit for detecting and determining the chassis type. The chassis detection circuit detects structural differences of the chassis to determine chassis type. The chassis detection circuit provides a signal indicative of whether an electrically conductive surface such as a flange surface on a grounding clip is electrically contacting a grounded structure of a chassis such as a hook structure of a planar plate to which a circuit board is secured. The chassis detection circuit can be implemented in a computer system where the determined chassis type is used in environmental monitoring programs or operations. Also, where the chassis type is indicative of the computer system type, the determined computer system type may be used for operations requiring computer system type identification.

Abstract: A transducer position sensing system, in a electromechanical drive, for determining transducer position. A sensor is mounted with a non-adjustable position and without absolute position accuracy, thereby lowering manufacturing costs. The position of the transducer at which the sensor switches states is accurately determined in a manufacturing test fixture and recorded in a permanent memory used by a drive controller. The drive controller can then accurately determine transducer position during subsequent initialization procedures.

Abstract: An engine system with a gear train to provide engine timing is disclosed. A technique to minimize backlash and noise caused by the gear train is included. An anti-backlash gear assembly useful to reduce backlash in the gear train is also disclosed. One disclosed gear assembly has at least two gear wheels with the circular thickness of the teeth of one gear wheel being less than the circular thickness of the other gear wheel. A gear assembly is also disclosed that has a bias torque of at least about 100 foot-pounds. A device carried on an anti-lash gear assembly to generally align teeth of the assembly for installation is also provided.

Abstract: A fan monitoring system for an electronics system or a computer system. The fan monitoring system includes a fan which produces a rotation signal, where the rotation signal is a function of the fan rotating. The fan monitoring system also includes a detection circuit responsive to the rotation signal and producing an operating signal indicative of the fan rotating. The fan monitoring system also includes a fan detection circuit having a primary connection point capable of being electrically coupled to the fan. The fan detection circuit provides a detection signal indicative of whether or not the fan is electrically coupled to the fan detection circuit. The fan monitoring system further includes an I/O circuit for receiving the fan detection signal and the operating signal. The I/O circuit providing I/O signals to a host computer system as determined by the operating signal and/or the detection signals.

Abstract: A communication system for coupling telephony or other signals to a broadband network such as a CATV network. The system transmits a multiplex of telephony signals in the forward band of the broadband network, with individual signals directed to an addressed subscriber. Telephony signals returning from subscribers upstream to a headend unit (HIU) are modulated onto the reverse band of the broadband network in a frequency division multiple access (FDMA) arrangement. The upstream modulated telephony signals are received at a telephony network interface at the HIU coupled to the broadband network. A group of reverse band modulated telephony signals are received at a group receiver or channelizer. The group receiver processes all upstream telephony signals within a selected spectral subband in the reverse band to apply a receiver matched filter with a weighted overlap and add circuit, and are then converted to baseband by an FFT circuit.

Abstract: The present invention provides a computer system which electronically and automatically detects the maximum rated operating frequency of a microprocessor installed in the computer system. The present invention also electronically and automatically detects, selects and generates a "common" external/internal operating clock frequency in a multiprocessor system when more than one microprocessor is installed in the computer system. More particularly, a computer system is disclosed which includes at least one microprocessor and a main memory coupled to each microprocessor. Each microprocessor includes an electronic stamp with a value of a maximum rated operating frequency for the microprocessor written therein. The computer system includes a clock generating section for electronically detecting the value of the maximum rated operating frequency of the each microprocessor and for selecting and generating an operating frequency for the computer system.

Abstract: A bus system is disclosed which includes first and second buses are coupled via an bus switch. The bus switch may be selectively turned on and off thus allowing the bus system to be electronically configured in a plurality of different configurations.

Abstract: A system for calibrating a magnetic tape drive for accurate movement of a tape head or drive motor accommodates mechanical and manufacturing inaccuracies. Motion is corrected through sensing variations from desired position or speed through operation of the drive in one continuous motion. These values may then be processed or filtered to remove non-repeatable effects and thus achieve appropriate correction in operation. The values may be written to a ROM in tabular format correlating position correction values with track number or adjusting speed coefficients for use during operation. For the tape head, actual position values are sensed in one substantially continuous motion of the tape head through a move command for faster calibration.

Abstract: A tape guide for a digital tape mini-cartridge providing decreased tape wander in a direction transverse to the intended path. The guide provides an increased area of tape having increased transverse stiffness without interfering with an adjacent drive wheel. In one embodiment, the guide is cylindrical and has a cylindrical cut-out to provide clearance for an adjacent cylindrical drive wheel. Preferably, the guide has top and bottom flanges. If a top flange of the guide is present, the cut-out continues through the top flange of the guide. The top flange of the guide may be relatively thin to fit below a top flange of the adjacent drive wheel. Alternatively, the top flange of the guide may have a larger cut-out to avoid interference with the top flange.