Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.

Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.

Abstract: Systems, computer program products, and methods are described herein for generating a graphical user interface including automatic and dynamic notifications. The present disclosure is configured to receive a trigger associated with a user account; identify user account data associated with the user account, wherein the user account data comprises at least one of a historical data or real time data; identify at least one similar user account based on the at least one similar user account comprising at least one similar historical data or similar real time data; generate a dynamic user account notification interface component, wherein the dynamic user account notification interface component comprises user account data; and transmit the dynamic user account notification interface component to a user device associated with the user account.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for using adversarial learning for fine-grained image search. An image search system receives a search query that includes an input image depicting an object. The search system generates, using a generator, a vector representation of the object in a normalized view. The generator was trained based on a set of reference images of known objects in multiple views, and feedback data received from an evaluator that indicates performance of the generator at generating vector representations of the known objects in the normalized view. The evaluator including a discriminator sub-module, a normalizer sub-module, and a semantic embedding sub-module that generate the feedback data. The image search system identifies, based on the vector representation of the object, a set of other images depicting the object, and returns at least one of the other images in response to the search query.

Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member.

Abstract: An integrated circuit includes: a gate dielectric; a first layer adjacent to the gate dielectric; a second layer adjacent to the first layer, the second layer comprising an amorphous material; a third layer adjacent to the second layer, the third layer comprising a crystalline material; and a source or drain at least partially adjacent to the third layer. In some cases, the crystalline material of the third layer is a first crystalline material, and the first layer comprises a second crystalline material, which may be the same as or different from the first crystalline material. In some cases, the gate dielectric includes a high-K dielectric material. In some cases, the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are part of a back-gate transistor structure (e.g., back-gate TFT), which may be part of a memory structure (e.g., located within an interconnect structure).

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

Abstract: Methods, systems and apparatus are provided for handling control flow structures in data-parallel architectures. A method includes receiving, by a processing unit (PU), a program for execution. The method further includes applying, by the PU, a branching solution to the program to obtain data on control flow structures of the program. The method further includes determining, by the PU and based at least in part on the obtained data, one or more control flow structures of the program to predicate. The method further includes applying, by the PU, predication to the one or more control flow structures of the program.

Abstract: Therapeutics and methods treating Alzheimer's disease or a pre-Alzheimer's disease condition in a patient comprising administering a pharmaceutical composition containing a therapeutically effective dose therapeutic, wherein the therapeutic contains a PRMT4 inhibitor, or a pharmaceutically acceptable salt, solvate, ester, amide, clathrate, stereoisomer, enantiomer, prodrug or analog thereof. According to a further embodiment, the PRMT4 inhibitor is one of TP-064 and SCFFBXO9.

Abstract: Described herein is a combination therapy for the treatment of a cancer in a subject. In one aspect, the therapy comprises selinexor and one or more second anti-cancer agents.

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.

Abstract: A media management system including an application layer, a system layer, and a solid state drive (SSD) storage layer. The application layer includes a media data analytics application configured to assign a classification code to a data file. The system layer is in communication with the application layer. The system layer includes a file system configured to issue a write command to a SSD controller. The write command includes the classification code of the data file. The SSD storage layer includes the SSD controller and erasable blocks. The SSD controller is configured to write the data file to one of the erasable blocks based on the classification code of the data file in the write command. In an embodiment, the SSD controller is configured to write the data file to one of the erasable blocks storing other data files also having the classification code.

Abstract: A multimedia query system is described that includes a multimedia capture system configured to capture raw multimedia data comprising at least one of raw video data or raw audio data, a metadata engine configured to extract one or more anchor points of metadata from the raw multimedia data and to store the one or more anchor points of metadata, wherein the anchor points of metadata includes references to respective portions of the raw multimedia data. The multimedia query system further includes a storage engine configured to store the raw multimedia data, a recall engine configured to receive a query and to apply the query to the one or more anchor points of metadata to identify one or more raw multimedia data candidates from the portions of the raw multimedia data, and a query engine configured to generate a response to the query based on the one or more raw multimedia data candidates.

Abstract: The present disclosure provides methods, systems and apparatus for handling control flow structures in data-parallel architectures. According to a first aspect, a method is provided. The method includes receiving, by a processing unit (PU), a program for execution. The method further includes applying, by the PU, a branching solution to the program to obtain data on control flow structures of the program. The method further includes determining, by the PU and based at least in part on the obtained data, one or more control flow structures of the program to predicate. The method further includes applying, by the PU, predication to the one or more control flow structures of the program.

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

Abstract: Transistor structures employing metal chalcogenide channel materials may be formed where a chalcogen is introduced into at least a portion of a precursor material that comprises reactive metal(s). The precursor material may be substantially metallic, or may be a metallic oxide (e.g., an oxide semiconductor). The metal(s) may be transition, Group II, Group III, Group V elements, or alloys thereof. An oxide of one or more such metals (e.g., IGZO) may be converted into a chalcogenide (e.g., IGZSx or IGZSex) having semiconducting properties. The chalcogenide formed in this manner may be only a few monolayers in thickness (and may be more thermally stable than many oxide semiconductors. Where not all of the precursor material is converted, a transistor structure may retain the precursor material, for example as part of a transistor channel or a gate dielectric. Backend transistors including metal chalcogenide channel materials may be fabricated over silicon CMOS circuitry.

Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.

Abstract: A multimedia query system is described that includes a multimedia capture system configured to capture raw multimedia data comprising at least one of raw video data or raw audio data, a metadata engine configured to extract one or more anchor points of metadata from the raw multimedia data and to store the one or more anchor points of metadata, wherein the anchor points of metadata includes references to respective portions of the raw multimedia data. The multimedia query system further includes a storage engine configured to store the raw multimedia data, a recall engine configured to receive a query and to apply the query to the one or more anchor points of metadata to identify one or more raw multimedia data candidates from the portions of the raw multimedia data, and a query engine configured to generate a response to the query based on the one or more raw multimedia data candidates.