Abstract: Novel tools and techniques are provided for implementing intent-based orchestration using network parsimony trees. In various embodiments, in response to receiving a request for network services that comprises desired characteristics and performance parameters for the requested network services without information regarding specific hardware, hardware type, location, or network, a computing system might generate a request-based parsimony tree based on the desired characteristics and performance parameters. The computing system might access, from a datastore, a plurality of network-based parsimony trees that are each generated based on measured network metrics, might compare the request-based parsimony tree with each of one or more network-based parsimony trees to determine a fitness score for each network-based parsimony tree, and might identify a best-fit network-based parsimony tree based on the fitness scores.

Abstract: Conventional email filtering services are not suitable for recognizing sophisticated malicious emails, and therefore may allow sophisticated malicious emails to reach inboxes by mistake. Introduced here are threat detection platforms designed to take an integrative approach to detecting security threats. For example, after receiving input indicative of an approval from an individual to access past email received by employees of an enterprise, a threat detection platform can download past emails to build a machine learning (ML) model that understands the norms of communication with internal contacts (e.g., other employees) and/or external contacts (e.g., vendors). By applying the ML model to incoming email, the threat detection platform can identify security threats in real time in a targeted manner.

Abstract: In one aspect, a leveling assembly for adjusting the levelness or skew angle of a bottom rail of a covering for an architectural structure includes at least one movable or slideable component configured to be moved or slid laterally relative to the bottom rail or a headrail of the covering to adjust the length(s) along which one or more of the lift cords extend within the bottom rail or headrail, which, in turn, adjusts the effective length of such lift cord(s) defined between the bottom rail and the headrail of the covering. Such adjustment of the effective length(s) of the lift cord(s) results in the horizontal orientation or skew angle of the bottom rail being varied, thereby allowing the levelness of the bottom rail to be adjusted, as desired.

Abstract: Embodiments provided herein, provide for variant IgG Fc polypeptides, dimeric molecules, pharmaceutical compositions, and methods that can be used to target at cells to modulate the activity of the same to treat disorders, such as autoimmune disorders or cancers.

Abstract: A media management system including an application layer, a system layer, and a solid state drive (SSD) storage layer. The application layer includes a media data analytics application configured to assign a classification code to a data file. The system layer is in communication with the application layer. The system layer includes a file system configured to issue a write command to a SSD controller. The write command includes the classification code of the data file. The SSD storage layer includes the SSD controller and erasable blocks. The SSD controller is configured to write the data file to one of the erasable blocks based on the classification code of the data file in the write command. In an embodiment, the SSD controller is configured to write the data file to one of the erasable blocks storing other data files also having the classification code.

Abstract: A microarray is designed to capture one or more molecules of interest at each of a plurality of sites on a substrate. The sites comprise base pads, such as polymer base pads, that promote the attachment of the molecules at the sites. The microarray may be made by one or more patterning techniques to create a layout of base pads in a desired pattern. Further, the microarrays may include features to encourage clonality at the sites.

Abstract: High energy density and long cycle life all solid-state electrolyte lithium-ion batteries use ceramic-polymer composite anodes which include a polymer matrix with ceramic nanoparticles, silicon-based anode active materials, conducting agents, lithium salts and plasticizer distributed in the matrix. The silicon-based anode active material are anode active particles formed by high energy milling a mixture of silicon, graphite, and metallic and/or non-metallic oxides. A polymer coating is applied to the particles. The networking structure of the electrolyte establishes an effective lithium-ion transport pathway in the electrode and strengthens the contact between the electrode layer and solid-state electrolyte resulting in higher lithium-ion battery cell cycling stability and long battery life.

Abstract: A customized template and method create a template that is customized for a particular patient based on a treatment plan of the patient to perform a brachytherapy treatment.

Abstract: The system obtains multiple unique identifiers associated with multiple UEs, where a unique identifier among the multiple unique identifiers identifies a UE among the multiple UEs. Based on the unique identifier, the system determines multiple technical capabilities associated with the multiple UEs. The system receives a request for one or more UEs, where the request includes a number of the one or more UEs and a desired technical capability associated with the one or more UEs, and where the request is specified at a level of abstraction that allows more than one UE among the multiple UEs to satisfy the request. Based on the request for the one or more UEs and the multiple technical capabilities associated with the multiple UEs, the system determines a subset of the multiple UEs satisfying the request, and sends a response to the request indicating the subset of the multiple UEs satisfying the request.

Abstract: In some cases, once Fast Reroute (FRR) has taken place (e.g., for MPLS protection), a further FRR is undesirable, and even detrimental. A mechanism to prevent a further FRR, once such a further FRR is determined to be potentially harmful, is described.

Abstract: A multimedia query system is described that includes a multimedia capture system configured to capture raw multimedia data comprising at least one of raw video data or raw audio data, a metadata engine configured to extract one or more anchor points of metadata from the raw multimedia data and to store the one or more anchor points of metadata, wherein the anchor points of metadata includes references to respective portions of the raw multimedia data. The multimedia query system further includes a storage engine configured to store the raw multimedia data, a recall engine configured to receive a query and to apply the query to the one or more anchor points of metadata to identify one or more raw multimedia data candidates from the portions of the raw multimedia data, and a query engine configured to generate a response to the query based on the one or more raw multimedia data candidates.

Abstract: The present disclosure provides methods, systems and apparatus for handling control flow structures in data-parallel architectures. According to a first aspect, a method is provided. The method includes receiving, by a processing unit (PU), a program for execution. The method further includes applying, by the PU, a branching solution to the program to obtain data on control flow structures of the program. The method further includes determining, by the PU and based at least in part on the obtained data, one or more control flow structures of the program to predicate. The method further includes applying, by the PU, predication to the one or more control flow structures of the program.

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

Abstract: Transistor structures employing metal chalcogenide channel materials may be formed where a chalcogen is introduced into at least a portion of a precursor material that comprises reactive metal(s). The precursor material may be substantially metallic, or may be a metallic oxide (e.g., an oxide semiconductor). The metal(s) may be transition, Group II, Group III, Group V elements, or alloys thereof. An oxide of one or more such metals (e.g., IGZO) may be converted into a chalcogenide (e.g., IGZSx or IGZSex) having semiconducting properties. The chalcogenide formed in this manner may be only a few monolayers in thickness (and may be more thermally stable than many oxide semiconductors. Where not all of the precursor material is converted, a transistor structure may retain the precursor material, for example as part of a transistor channel or a gate dielectric. Backend transistors including metal chalcogenide channel materials may be fabricated over silicon CMOS circuitry.

Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.

Abstract: A multimedia query system is described that includes a multimedia capture system configured to capture raw multimedia data comprising at least one of raw video data or raw audio data, a metadata engine configured to extract one or more anchor points of metadata from the raw multimedia data and to store the one or more anchor points of metadata, wherein the anchor points of metadata includes references to respective portions of the raw multimedia data. The multimedia query system further includes a storage engine configured to store the raw multimedia data, a recall engine configured to receive a query and to apply the query to the one or more anchor points of metadata to identify one or more raw multimedia data candidates from the portions of the raw multimedia data, and a query engine configured to generate a response to the query based on the one or more raw multimedia data candidates.

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

Abstract: Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.

Abstract: An integrated circuit includes: a gate dielectric; a first layer adjacent to the gate dielectric; a second layer adjacent to the first layer, the second layer comprising an amorphous material; a third layer adjacent to the second layer, the third layer comprising a crystalline material; and a source or drain at least partially adjacent to the third layer. In some cases, the crystalline material of the third layer is a first crystalline material, and the first layer comprises a second crystalline material, which may be the same as or different from the first crystalline material. In some cases, the gate dielectric includes a high-K dielectric material. In some cases, the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are part of a back-gate transistor structure (e.g., back-gate TFT), which may be part of a memory structure (e.g., located within an interconnect structure).

Abstract: Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.