Patents by Inventor Kevin Lin

Kevin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10971393
    Abstract: An apparatus is provided which includes: a first stack including a lower, a middle, and an upper layer of conductive material with insulator layers therebetween, and a second stack including the middle and upper layers with one of the insulator layers therebetween. In an example, a first of the insulator layers has a lower breakdown voltage than a second of the insulator layers. The apparatus further includes a first via over the first stack, wherein the first via is in contact with a pair of the lower, middle and upper layers that have the first of the insulator layers therebetween. The apparatus further includes a second via over the second stack, wherein the second via extends through the upper layer and is in contact with the middle layer. In an example, the second via is isolated from a sidewall of the upper layer by a spacer.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventor: Kevin Lin
  • Publication number: 20210050261
    Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 18, 2021
    Inventors: Kevin LIN, Robert L. BRISTOL, Richard E. SCHENKER
  • Patent number: 10916499
    Abstract: Systems and methods for maskless gap (for example, air gap) integration into multilayer interconnects having one or more interconnect lines (for example, metal interconnect lines) embedded in a dielectric layer of the interconnects are described. In various embodiments, the described systems and methods may serve to reduce electrical shorting between adjacent vias in the interconnects. In one embodiment, a spacer layer may be provided to mask portions of an interlayer dielectric (ILD) in the interconnect. These masked portions of the ILD can protect regions between adjacent interconnect lines (for example, metal interconnect lines) from electrical shorting during subsequent metal layer depositions, for example, during a fabrication sequence of the interconnects. Further, the vias may enclose a gap (for example, an air gap) without the need for additional masking steps. Further, such gaps may be inherently self-aligned to the vias and/or spacer layers.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Manish Chandhok
  • Patent number: 10907145
    Abstract: Ligands and methods for selectively binding hypermethylated DNA from a sample. The ligands include a CG-region binding molecule-conjugated resin derived from the aminoglycoside antibiotic amikacin. Furthermore, the CG-region binding molecule may be conjugated to the resin with a crosslinker and/or may be modified with one or more of long chain and short chain alkyl, aryl, piperazinyl, piperidyl, and pyrrolidyl groups. Such ligands are used in methods for contacting a sample to thereby selectively bind hypermethylated DNA.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: February 2, 2021
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Kaushal Rege, Kevin Lin, Sudhakar Godeshala, Taraka Sai Pavan Grandhi
  • Publication number: 20210005511
    Abstract: Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 7, 2021
    Inventors: Kevin LIN, Robert L. BRISTOL, Richard E. SCHENKER
  • Publication number: 20200411678
    Abstract: A semiconductor-on-insulator (SOI) substrate with a compliant substrate layer advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N devices (e.g., III-N HFETs) may be formed. The compliant layer may be (111) silicon, for example. The SOI substrate may further include another layer that may have one or more of lower electrical resistivity, greater thickness, or a different crystal orientation relative to the compliant substrate layer. A SOI substrate may include a (100) silicon layer advantageous for integrating Group IV devices (e.g., Si FETs), for example. To reduce parasitic coupling between an HFET and a substrate layer of relatively low electrical resistivity, one or more layers of the substrate may be removed within a region below the HFETs. Once removed, the resulting void may be backfilled with another material, or the void may be sealed, for example during back-end-of-line processing.
    Type: Application
    Filed: September 28, 2017
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Kevin Lin, Paul Fischer
  • Patent number: 10867853
    Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Robert L. Bristol, Richard E. Schenker
  • Publication number: 20200388685
    Abstract: Transistor structures employing metal chalcogenide channel materials may be formed where a chalcogen is introduced into at least a portion of a precursor material that comprises reactive metal(s). The precursor material may be substantially metallic, or may be a metallic oxide (e.g., an oxide semiconductor). The metal(s) may be transition, Group II, Group III, Group V elements, or alloys thereof. An oxide of one or more such metals (e.g., IGZO) may be converted into a chalcogenide (e.g., IGZSx or IGZSex) having semiconducting properties. The chalcogenide formed in this manner may be only a few monolayers in thickness (and may be more thermally stable than many oxide semiconductors. Where not all of the precursor material is converted, a transistor structure may retain the precursor material, for example as part of a transistor channel or a gate dielectric. Backend transistors including metal chalcogenide channel materials may be fabricated over silicon CMOS circuitry.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Ashish Agarwal, Urusa Alaan, Christopher Jezewski, Kevin Lin, Carl Naylor
  • Publication number: 20200364303
    Abstract: Apparatuses, systems, and techniques to transfer grammar between sentences. In at least one embodiment, one or more first sentences are translated into one or more second sentences having different grammar using one or more neural networks.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 19, 2020
    Inventors: Ming-Yu Liu, Kevin Lin
  • Publication number: 20200357929
    Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.
    Type: Application
    Filed: September 29, 2017
    Publication date: November 12, 2020
    Applicant: INTEL CORPORATION
    Inventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
  • Publication number: 20200350184
    Abstract: A structure, comprising an island comprising a III-N material. The island extends over a substrate and has a sloped sidewall. A cap comprising a III-N material extends laterally from a top surface and overhangs the sidewall of the island. A device, such as a transistor, light emitting diode, or resonator, may be formed within, or over, the cap.
    Type: Application
    Filed: September 27, 2017
    Publication date: November 5, 2020
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul Fischer, Kevin Lin
  • Publication number: 20200351161
    Abstract: Techniques for implementing a provisional mode in a multi-mode network device (i.e., a network device that supports at least first and second modes of operation) are provided. According to one embodiment, the network device can receive, while running in the first mode, a request to enter the second mode. In response to the request, the network device can enter a third mode that is a provisional version of the second mode. Then, while running in the third mode, the network device can accept one or more configuration commands or settings for the second mode while simultaneously processing live network traffic according to the first mode.
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Applicant: ARRIS Enterprises LLC
    Inventors: Kwun-Nan Kevin Lin, Tian Lei
  • Patent number: 10804141
    Abstract: Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Robert L. Bristol, Richard E. Schenker
  • Publication number: 20200321246
    Abstract: Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.
    Type: Application
    Filed: December 27, 2017
    Publication date: October 8, 2020
    Applicant: Intel Corporation
    Inventors: Kevin Lin, Christopher J. Jezewski
  • Publication number: 20200303238
    Abstract: Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 24, 2020
    Inventors: Ehren MANNEBACH, Aaron LILAK, Rishabh MEHANDRU, Hui Jae YOO, Patrick MORROW, Kevin LIN
  • Publication number: 20200279806
    Abstract: Integrated circuit (IC) interconnect lines having improved electromigration resistance. Multi-patterning may be employed to define a first mask pattern. The first mask pattern may be backfilled and further patterned based on a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of material underlying openings defined in the second mask layer that exceed the threshold are removed. First trenches in an underlying dielectric material layer may be etched based on a union of the remainder of the first mask layer and the partially occluded second mask layer. The first trenches may then be backfilled with a first conductive material to form first line segments. Additional trenches in the underlayer may then be etched and backfilled with a second conductive material to form second line segments that are coupled together by the first line segments.
    Type: Application
    Filed: December 27, 2017
    Publication date: September 3, 2020
    Applicant: Intel Corporation
    Inventors: Kevin Lin, Christopher J. Jezewski, Manish Chandhok
  • Publication number: 20200272812
    Abstract: A machine accesses a training data set comprising multiple real images and multiple synthetic images. The machine trains a joint prediction module to predict joint locations in visual data using the multiple real images. The machine trains a part affinity field prediction module to identify adjacent joints in visual data using the multiple real images. The machine trains the joint prediction module to predict joint locations in visual data using the multiple synthetic images. The machine trains the part affinity field prediction module to identify adjacent joints in visual data using the multiple synthetic images. The machine trains a body part prediction module to identify body parts in visual data using the multiple synthetic images. The machine provides a trained human body part segmentation module comprising the trained joint prediction module, the trained part affinity field prediction module, and the trained body part prediction module.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 27, 2020
    Inventors: Lijuan Wang, Zicheng Liu, Kevin Lin, Kun Luo
  • Publication number: 20200273746
    Abstract: An apparatus is provided which includes: a first stack including a lower, a middle, and an upper layer of conductive material with insulator layers therebetween, and a second stack including the middle and upper layers with one of the insulator layers therebetween. In an example, a first of the insulator layers has a lower breakdown voltage than a second of the insulator layers. The apparatus further includes a first via over the first stack, wherein the first via is in contact with a pair of the lower, middle and upper layers that have the first of the insulator layers therebetween. The apparatus further includes a second via over the second stack, wherein the second via extends through the upper layer and is in contact with the middle layer. In an example, the second via is isolated from a sidewall of the upper layer by a spacer.
    Type: Application
    Filed: December 27, 2017
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventor: Kevin Lin
  • Publication number: 20200272888
    Abstract: A computing system is provided. The computing system includes a processor configured to execute a convolutional neural network that has been trained, the convolutional neural network including a backbone network that is a concatenated pyramid network, a plurality of first head neural networks, and a plurality of second head neural networks. At the backbone network, the processor is configured to receive an input image as input and output feature maps extracted from the input image. The processor is configured to: process the feature maps using each of the first head neural networks to output corresponding keypoint heatmaps; process the feature maps using each of the second head neural networks to output corresponding part affinity field heatmaps; link the keypoints into one or more instances of virtual skeletons using the part affinity fields; and output the instances of the virtual skeletons.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 27, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Lijuan WANG, Kevin LIN, Zicheng LIU, Kun LUO
  • Patent number: 10754730
    Abstract: Provided are a computer program product, system, and method for copying point-in-time data in a storage to a point-in-time copy data location in advance of destaging data to the storage. A point-in-time copy is created to maintain tracks in a source storage unit as of a point-in-time. A source copy data structure indicates tracks in the source storage unit to copy from the storage to a point-in-time data location. An update to write to a source track is received and a determination is made as to whether the source copy data structure indicates to copy the source track from the storage to the point-in-time data location. The update is written to a cache. A copy operation is initiated to copy the source track from the storage to the point-in-time data location asynchronous before the source track is destaged from the cache to the storage unit.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Theresa M. Brown, Kevin Lin, David Fei, Nedlaya Y. Francisco