Patents by Inventor Kevin Lin

Kevin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200272888
    Abstract: A computing system is provided. The computing system includes a processor configured to execute a convolutional neural network that has been trained, the convolutional neural network including a backbone network that is a concatenated pyramid network, a plurality of first head neural networks, and a plurality of second head neural networks. At the backbone network, the processor is configured to receive an input image as input and output feature maps extracted from the input image. The processor is configured to: process the feature maps using each of the first head neural networks to output corresponding keypoint heatmaps; process the feature maps using each of the second head neural networks to output corresponding part affinity field heatmaps; link the keypoints into one or more instances of virtual skeletons using the part affinity fields; and output the instances of the virtual skeletons.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 27, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Lijuan WANG, Kevin LIN, Zicheng LIU, Kun LUO
  • Patent number: 10754730
    Abstract: Provided are a computer program product, system, and method for copying point-in-time data in a storage to a point-in-time copy data location in advance of destaging data to the storage. A point-in-time copy is created to maintain tracks in a source storage unit as of a point-in-time. A source copy data structure indicates tracks in the source storage unit to copy from the storage to a point-in-time data location. An update to write to a source track is received and a determination is made as to whether the source copy data structure indicates to copy the source track from the storage to the point-in-time data location. The update is written to a cache. A copy operation is initiated to copy the source track from the storage to the point-in-time data location asynchronous before the source track is destaged from the cache to the storage unit.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Theresa M. Brown, Kevin Lin, David Fei, Nedlaya Y. Francisco
  • Patent number: 10740203
    Abstract: A plurality of tracks that are to be copied to a backup volume are aggregated in a container data structure. The plurality of tracks are stored physically contiguously in a single Redundant Array of Independent Disks (RAID) stride. Mapping metadata is updated in the backup volume to indicate how logical tracks of the backup volume correspond to physical tracks stored in the RAID stride.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Theresa M. Brown, Kevin Lin, Dave Fei, Gail Spear, Clint A. Hardy, Karl A. Nielsen
  • Publication number: 20200252984
    Abstract: A system and method of data communication is provided for use in a wireless communication system. The wireless communication system includes a base station, a relay user equipment (UE) and an out of coverage UE (OOC-UE). The method includes receiving, at the relay UE and from the base station, a relay cycle configuration, the relay cycle configuration defining a relay cycle including a first time period for device to device (D2D) communication, and a second time period for cellular communication. The method then includes receiving, at the relay UE by D2D communication, within the first time period and from the out of coverage UE (OOC-UE), relay data, and providing, from the relay UE by cellular communication, within the second time period and to the BS, the relay data.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Applicant: NEC CORPORATION
    Inventors: Phong NGUYEN, Kevin LIN
  • Publication number: 20200252918
    Abstract: There is provided a signaling method for use in an advanced wireless communication network (100) that supports a first duplex mode, a second duplex mode different to the first duplex mode, and carrier aggregation of the first second duplex modes. This method includes configuring a UE (104-106) for data communication with the network (100) through a first access node (101) as a PCell, on the first duplex mode and with a first transmission mode (TM) including one or more transport blocks (TBs). This method also includes configuring the UE (104-106) for data communication with the network (100) through a second access node (103) as a SCell, on the second duplex mode and with a second TM including one or more TBs. The second TM associated with the second access node (103) is configured independently of the first TM associated with the first access node (101).
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Applicant: NEC CORPORATION
    Inventors: Yuanrong LAN, Kevin Lin, Phong NGUYEN
  • Patent number: 10721123
    Abstract: Techniques for implementing a provisional mode in a multi-mode network device (i.e., a network device that supports at least first and second modes of operation) are provided. According to one embodiment, the network device can receive, while running in the first mode, a request to enter the second mode. In response to the request, the network device can enter a third mode that is a provisional version of the second mode. Then, while running in the third mode, the network device can accept one or more configuration commands or settings for the second mode while simultaneously processing live network traffic according to the first mode.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: July 21, 2020
    Assignee: ARRIS Enterprises LLC
    Inventors: Kwun-Nan Kevin Lin, Tian Lei
  • Publication number: 20200227348
    Abstract: An apparatus is provided, which includes a stack of a first plurality of layers interleaved with a second plurality of layers. In an example, the first plurality of layers includes conductive material, and the second plurality of layers includes insulating material. In an example, the first plurality of layers includes an upper layer and lower layer. A first via may extend through at least a portion of the stack, where the first via may be in contact with the upper layer and the lower layer. A second via may extend through at least a portion of the stack, where the second via may be isolated from the upper layer and lower layer.
    Type: Application
    Filed: December 27, 2017
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventor: Kevin Lin
  • Publication number: 20200211974
    Abstract: A multilayer conductive line is disclosed. The multilayer conductive line includes a dielectric layer, a Ta barrier layer on the dielectric layer and a superlattice on the Ta barrier layer. The superlattice includes a plurality of interleaved ferromagnetic and non-ferromagnetic material.
    Type: Application
    Filed: December 26, 2018
    Publication date: July 2, 2020
    Inventors: Noriyuki SATO, Kevin LIN, Kevin O'BRIEN, Hui Jae YOO
  • Publication number: 20200194338
    Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Carl NAYLOR, Ashish AGRAWAL, Kevin LIN, Abhishek Sharma, Mauro KOBRINSKY, Christopher JEZEWSKI, Urusa ALAAN
  • Publication number: 20200194376
    Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Carl NAYLOR, Ashish AGRAWAL, Kevin LIN, Abhishek SHARMA, Mauro KOBRINSKY, Christopher JEZEWSKI, Urusa ALAAN
  • Publication number: 20200185226
    Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 11, 2020
    Applicant: Intel Corporation
    Inventors: Kevin LIN, Rahim KASIM, Manish CHANDHOK, Florian Gstrein
  • Publication number: 20200185532
    Abstract: A transistor structure includes a layer of active material on a base. The base can be insulator material in some cases. The layer has a channel region between a source region and a drain region. A gate structure is in contact with the channel region and includes a gate electrode and a gate dielectric, where the gate dielectric is between the gate electrode and the active material. An electrical contact is on one or both of the source region and the drain region. The electrical contact has a larger portion in contact with a top surface of the active material and a smaller portion extending through the layer of active material into the base. The active material may be, for example, a transition metal dichalcogenide (TMD) in some embodiments.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 11, 2020
    Applicant: INTEL CORPORATION
    Inventors: Kevin Lin, Abhishek Sharma, Carl Naylor, Urusa Alaan, Christopher Jezewski, Ashish Agrawal
  • Patent number: 10667311
    Abstract: A system and method of data communication is provided for use in a wireless communication system. The wireless communication system includes a base station, a relay user equipment (UE) and an out of coverage UE (OOC-UE). The method includes receiving, at the relay UE and from the base station, a relay cycle configuration, the relay cycle configuration defining a relay cycle including a first time period for device to device (D2D) communication, and a second time period for cellular communication. The method then includes receiving, at the relay UE by D2D communication, within the first time period and from the out of coverage UE (OOC-UE), relay data, and providing, from the relay UE by cellular communication, within the second time period and to the BS, the relay data.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: May 26, 2020
    Assignee: NEC CORPORATION
    Inventors: Phong Nguyen, Kevin Lin
  • Patent number: 10645684
    Abstract: There is provided a signalling method for use in an advanced wireless communication network (100) that supports a first duplex mode, a second duplex mode different to the first duplex mode, and carrier aggregation of the first second duplex modes. This method includes configuring a UE (104-106) for data communication with the network (100) through a first access node (101) as a PCell, on the first duplex mode and with a first transmission mode (TM) including one or more transport blocks (TBs). This method also includes configuring the UE (104-106) for data communication with the network (100) through a second access node (103) as a SCell, on the second duplex mode and with a second TM including one or more TBs. The second TM associated with the second access node (103) is configured independently of the first TM associated with the first access node (101).
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: May 5, 2020
    Assignee: NEC CORPORATION
    Inventors: Yuanrong Lan, Kevin Lin, Phong Nguyen
  • Patent number: 10593627
    Abstract: Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a plurality of openings are formed in a first sacrificial material layer. Conductive vias and dielectric pillars may be formed in the openings. A second sacrificial material layer may then be formed over the pillars, the vias, and the first sacrificial material layer. In an embodiment, a permeable etchstop layer is formed over a top surface of the second sacrificial layer. Embodiments then include forming an interconnect line in the second sacrificial material layer. In an embodiment, the first and second sacrificial material layers are removed through the permeable etchstop layer after the interconnect line has been formed. According to an embodiment, the permeable etchstop layer may then be stuffed with a fill material in order to harden the permeable etchstop layer.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Kanwal Jit Singh, Kevin Lin, Robert Lindsey Bristol
  • Publication number: 20200081792
    Abstract: Provided are a computer program product, system, and method for copying point-in-time data in a storage to a point-in-time copy data location in advance of destaging data to the storage. A point-in-time copy is created to maintain tracks in a source storage unit as of a point-in-time. A source copy data structure indicates tracks in the source storage unit to copy from the storage to a point-in-time data location. An update to write to a source track is received and a determination is made as to whether the source copy data structure indicates to copy the source track from the storage to the point-in-time data location. The update is written to a cache. A copy operation is initiated to copy the source track from the storage to the point-in-time data location asynchronous before the source track is destaged from the cache to the storage unit.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 12, 2020
    Inventors: Theresa M. Brown, Kevin Lin, David Fei, Nedlaya Y. Francisco
  • Publication number: 20200081808
    Abstract: A plurality of tracks that are to be copied to a backup volume are aggregated in a container data structure. The plurality of tracks are stored physically contiguously in a single Redundant Array of Independent Disks (RAID) stride. Mapping metadata is updated in the backup volume to indicate how logical tracks of the backup volume correspond to physical tracks stored in the RAID stride.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 12, 2020
    Inventors: Theresa M. BROWN, Kevin LIN, Dave FEI, Gail SPEAR, Clint A. HARDY, Karl A. NIELSEN
  • Publication number: 20200081629
    Abstract: Provided are techniques for performing a recovery copy command to restore a safeguarded copy backup to a production volume. In response to receiving a recovery copy command, a production target data structure is created. A read operation is received for data for a storage location. In response to determining that the data for the storage location is in a cache of a host and a generation number is greater than a recovery generation number, the data is read from the cache. In response to determining at least one of that the data for the storage location is not in the cache and that the generation number is not greater than the recovery generation number, the data is read from one of the production volume and a backup volume based on a value of an indicator for the storage location in the production target data structure.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 12, 2020
    Inventors: Theresa M. Brown, Nedlaya Y. Francisco, Nicolas M. Clayton, Mark L. Lipets, Carol S. Mellgren, Gregory E. McBride, David Fei, Kevin Lin
  • Publication number: 20200066521
    Abstract: A computing device including tight pitch features and a method of fabricating a computing device using colored spacer formation is disclosed. The computing device includes a memory and an integrated circuit coupled to the memory. The integrated circuit includes a first multitude of features above a substrate. The integrated circuit die includes a second multitude of features above the substrate. The first multitude of features and the second multitude of features are same features disposed in a first direction. The first multitude of features interleave with the second multitude of features. The first multitude of features has a first size and the second multitude of features has a second size.
    Type: Application
    Filed: March 31, 2017
    Publication date: February 27, 2020
    Inventors: Kevin LIN, Rami HOURANI, Elliot N. TAN, Manish CHANDHOK, Anant H. JAHAGIRDAR, Robert L. BRISTOL, Richard E. SCHENKER, Aaron Douglas LILAK
  • Patent number: 10553532
    Abstract: Embodiments of the invention include interconnect structures with overhead vias and through vias that are self-aligned with interconnect lines and methods of forming such structures. In an embodiment, an interconnect structure is formed in an interlayer dielectric (ILD). One or more first interconnect lines may be formed in the ILD. The interconnect structure may also include one or more second interconnect lines in the ILD that arranged in an alternating pattern with the first interconnect lines. Top surfaces of each of the first and second interconnect lines may be recessed below a top surface of the ILD. The interconnect structure may include a self-aligned overhead via formed over one or more of the first interconnect lines or over one or more of the second interconnect lines. In an embodiment, a top surface of the self-aligned overhead via is substantially coplanar with a top surface of the ILD.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Richard E. Schenker, Manish Chandhok, Robert L. Bristol, Mauro J. Kobrinsky, Kevin Lin