Patents by Inventor Kevin Lin

Kevin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200027827
    Abstract: Systems and methods for maskless gap (for example, air gap) integration into multilayer interconnects having one or more interconnect lines (for example, metal interconnect lines) embedded in a dielectric layer of the interconnects are described. In various embodiments, the described systems and methods may serve to reduce electrical shorting between adjacent vias in the interconnects. In one embodiment, a spacer layer may be provided to mask portions of an interlayer dielectric (ILD) in the interconnect. These masked portions of the ILD can protect regions between adjacent interconnect lines (for example, metal interconnect lines) from electrical shorting during subsequent metal layer depositions, for example, during a fabrication sequence of the interconnects. Further, the vias may enclose a gap (for example, an air gap) without the need for additional masking steps. Further, such gaps may be inherently self-aligned to the vias and/or spacer layers.
    Type: Application
    Filed: September 30, 2016
    Publication date: January 23, 2020
    Applicant: Intel Corporation
    Inventors: Kevin LIN, Manish CHANDHOK
  • Publication number: 20200006261
    Abstract: An integrated circuit structure comprises one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 ?m. An air gap is in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventor: Kevin LIN
  • Publication number: 20200006427
    Abstract: An integrated circuit structure includes a first material block comprising a first block insulator layer and a first multilayer stack on the first block insulator layer, the first multilayer stack comprising interleaved pillar electrodes and insulator layers. A second material block is stacked on the first material block and comprises a second block insulator layer, and a second multilayer stack on the second block insulator layer, the second multilayer stack comprising interleaved pillar electrodes and insulator layers. At least one pillar extends through the first material block and the second material block, wherein the at least one pillar has a top width at a top of the first and second material blocks that is greater than a bottom width at a bottom of the first and second material blocks.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Noriyuki SATO, Kevin O'BRIEN, Eungnak HAN, Manish CHANDHOK, Gurpreet SINGH, Nafees KABIR, Kevin LIN, Rami HOURANI, Abhishek SHARMA, Hui Jae YOO
  • Publication number: 20200006138
    Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Kevin LIN, Sudipto NASKAR, Manish CHANDHOK, Miriam RESHOTKO, Rami HOURANI
  • Publication number: 20190393036
    Abstract: Metal spacer-based approaches for fabricating conductive lines/interconnects are described. In an example, an integrated circuit structure includes a substrate. A first spacer pattern is on the substrate, the first spacer pattern comprising a first plurality of dielectric spacers and a first plurality of metal spacers formed along sidewalls of the first plurality of dielectric spacers, wherein the first plurality of dielectric spacers have a first width (W1). A second spacer pattern is on the substrate, where the second spacer pattern interleaved with the first spacer pattern, the second spacer pattern comprising a second plurality of dielectric spacers having a second width (W2) formed on exposed sidewalls of the first plurality of metal spacers, and a second plurality of metal spacers formed on exposed sidewalls of the second plurality of dielectric spacers.
    Type: Application
    Filed: June 20, 2018
    Publication date: December 26, 2019
    Inventors: Kevin LIN, Charles WALLACE
  • Publication number: 20190393147
    Abstract: An integrated circuit structure comprises a first and second conductive structures formed in an interlayer dielectric (ILD) of a metallization stack over a substrate. The first conductive structure comprises a first conductive line, and first dummy structures located adjacent to one or more sides of the first conductive line, wherein the first dummy structures comprise respective arrays of dielectric core segments having a Young's modulus larger than the Young's modulus of the ILD, the dielectric core segments being approximately 1-3 microns in width and spaced apart by approximately 1-3 microns. The second conductive structure formed in the ILD comprises a conductive surface and second dummy structures formed in the conductive surface, where the second dummy structures comprising an array of conductive pillars.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventor: Kevin LIN
  • Publication number: 20190393298
    Abstract: An integrated circuit structure comprises a first dielectric layer disposed above a substrate. The integrated circuit structure comprises an interconnect structure comprising a first interconnect on a first metal layer, a second interconnect on a second metal layer, and a via connecting the first interconnect and the second interconnect, the first interconnect being on or within the first dielectric layer. A metal-insulator-metal (MIM) capacitor is formed in or on the first dielectric layer in the first metal layer adjacent to the interconnect structure. The MIM capacitor comprises a bottom electrode plate comprising a first low resistivity material, an insulator stack on the bottom electrode plate, the insulator stack comprising at least one of an etch stop layer and a high-K dielectric layer; and a top electrode plate on the insulator stack, the top electrode plate comprising a second low resistivity material.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Kevin LIN, Han Wui THEN
  • Publication number: 20190385897
    Abstract: An integrated circuit die, a semiconductor structure, and a method of fabricating the semiconductor structure are disclosed. The integrated circuit die includes a substrate and a first anchor and a second anchor disposed on the substrate in a first plane. The integrated circuit die also includes a first wire disposed on the first anchor in the first plane, a third wire disposed on the second anchor in the first plane, and a second wire and a fourth wire suspended above the substrate in the first plane. The second wire is disposed between the first wire and the third wire and the third wire is disposed between the second wire and the fourth wire. The integrated circuit die further includes a dielectric material disposed between upper portions of the first wire, the second wire, the third wire, and the fourth wire to encapsulate an air gap.
    Type: Application
    Filed: December 28, 2016
    Publication date: December 19, 2019
    Inventors: Manish CHANDHOK, Sudipto NASKAR, Stephanie A. BOJARSKI, Kevin LIN, Marie KRYSAK, Tristan A. TRONIC, Hui Jae YOO, Jeffery D. BIELEFELD, Jessica M. TORRES
  • Publication number: 20190362191
    Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for using adversarial learning for fine-grained image search. An image search system receives a search query that includes an input image depicting an object. The search system generates, using a generator, a vector representation of the object in a normalized view. The generator was trained based on a set of reference images of known objects in multiple views, and feedback data received from an evaluator that indicates performance of the generator at generating vector representations of the known objects in the normalized view. The evaluator including a discriminator sub-module, a normalizer sub-module, and a semantic embedding sub-module that generate the feedback data. The image search system identifies, based on the vector representation of the object, a set of other images depicting the object, and returns at least one of the other images in response to the search query.
    Type: Application
    Filed: May 22, 2018
    Publication date: November 28, 2019
    Inventors: Kevin Lin, Fan Yang, Qiaosong Wang, Robinson Piramuthu
  • Publication number: 20190355665
    Abstract: Embodiments include an interconnect structure and methods of forming an interconnect structure. In an embodiment, the interconnect structure comprises a semiconductor substrate and an interlayer dielectric (ILD) over the semiconductor substrate. In an embodiment, an interconnect layer is formed over the ILD. In an embodiment, the interconnect layer comprises a first interconnect and a second interconnect. In an embodiment the interconnect structure comprises an electrically insulating plug that separates the first interconnect and the second interconnect. In an embodiment an uppermost surface of the electrically insulating plug is above an uppermost surface of the interconnect layer.
    Type: Application
    Filed: May 21, 2018
    Publication date: November 21, 2019
    Inventors: Ehren MANNEBACH, Kevin LIN, Richard VREELAND
  • Publication number: 20190326214
    Abstract: Methods/structures of forming thin film resistors using interconnect liner materials are described. Those methods/structures may include forming a first liner in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate. Forming a second liner in a second trench, wherein the second trench is adjacent the first trench, forming an interconnect material on the first liner in the first trench, adjusting a resistance value of the second liner, forming a first contact structure on a top surface of the interconnect material, and forming a second contact structure on the second liner.
    Type: Application
    Filed: December 29, 2016
    Publication date: October 24, 2019
    Applicant: Intel Corporation
    Inventors: Kevin Lin, Christopher J. Jezewski, Richard F. Vreeland, Tristan A. Tronic
  • Patent number: 10427272
    Abstract: A method of polishing includes polishing a layer of a substrate, monitoring the layer of the substrate with an in-situ monitoring system to generate signal that depends on a thickness of the layer, filtering the signal to generate a filtered signal, determining an adjusted threshold value from an original threshold value and a time delay value representative of time required for filtering the signal, and triggering a polishing endpoint when the filtered signal crosses the adjusted threshold value.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: October 1, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Kun Xu, Kevin Lin, Ingemar Carlsson, Shih-Haur Shen, Tzu-Yu Liu
  • Publication number: 20190294511
    Abstract: Consistency groups are asynchronously copied to a remote computational device, from a local computational device, wherein point in time copy operations are performed at the local computational device while the consistency groups are being asynchronously copied to the remote computational device. Indicators are stored at the remote computational device to identify those point in time copy operations that are to be restored as part of a recovery operation performed at the remote computational device in response to a failure of the local computational device.
    Type: Application
    Filed: June 13, 2019
    Publication date: September 26, 2019
    Inventors: Theresa M. Brown, Nicolas M. Clayton, Nedlaya Y. Francisco, Theodore T. Harris, JR., Kevin Lin, Gregory E. McBride, Carol S. Mellgren, Raul E. Saba, Matthew Sanchez
  • Patent number: 10425377
    Abstract: Systems, methods, and non-transitory computer readable media are configured to monitor event information relating to an event broadcasted to an audience of a social networking system. The event information can include users who are participating in the event. It can be determined that a predetermined entity is participating in the event. A notification that the predetermined entity is participating in the event is provided during the event to at least one of a broadcaster of the event and a user participating in the event.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: September 24, 2019
    Assignee: Facebook, Inc.
    Inventors: Kevin Lin, Ryan Lin
  • Publication number: 20190287813
    Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 19, 2019
    Inventors: Kevin LIN, Robert Lindsey BRISTOL, Alan M. MYERS
  • Publication number: 20190267961
    Abstract: The RF filters used in conventional mobile devices often include resonator structures, which often require free-standing air-gap structure to prevent mechanical vibrations of the resonator from being damped by a bulk material. A method for fabricating a resonator structure comprises depositing a non-conformal thin-film to the resonator structure to seal air gap cavities in the resonator structure.
    Type: Application
    Filed: December 29, 2016
    Publication date: August 29, 2019
    Inventors: Kevin LIN, Kimin JUN, Edris MOHAMMED
  • Publication number: 20190254093
    Abstract: A system and method of data communication is provided for use in a wireless communication system. The wireless communication system includes a base station, a relay user equipment (UE) and an out of coverage UE (OOC-UE). The method includes receiving, at the relay UE and from the base station, a relay cycle configuration, the relay cycle configuration defining a relay cycle including a first time period for device to device (D2D) communication, and a second time period for cellular communication. The method then includes receiving, at the relay UE by D2D communication, within the first time period and from the out of coverage UE (OOC-UE), relay data, and providing, from the relay UE by cellular communication, within the second time period and to the BS, the relay data.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 15, 2019
    Applicant: NEC CORPORATION
    Inventors: Phong NGUYEN, Kevin LIN
  • Patent number: 10366950
    Abstract: Embodiments of the invention include an interconnect structure with a via and methods of forming such structures. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD). A first interconnect line and a second interconnect line extend into the first ILD. According to an embodiment, a second ILD is positioned over the first interconnect line and the second interconnect line. A via may extend through the second ILD and electrically coupled to the first interconnect line. Additionally, embodiments of the invention include a portion of a bottom surface of the via being positioned over the second interconnect line. However, an isolation layer may be positioned between the bottom surface of the via and a top surface of the second interconnect line, according to an embodiment of the invention.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Robert Lindsey Bristol, James M. Blackwell, Rami Hourani
  • Patent number: 10366903
    Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Robert Lindsey Bristol, Alan M. Myers
  • Patent number: 10360112
    Abstract: Consistency groups are asynchronously copied to a remote computational device, from a local computational device, wherein point in time copy operations are performed at the local computational device while the consistency groups are being asynchronously copied to the remote computational device. Indicators are stored at the remote computational device to identify those point in time copy operations that are to be restored as part of a recovery operation performed at the remote computational device in response to a failure of the local computational device.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Theresa M. Brown, Nicolas M. Clayton, Nedlaya Y. Francisco, Theodore T. Harris, Jr., Kevin Lin, Gregory E. McBride, Carol S. Mellgren, Raul E. Saba, Matthew Sanchez