Abstract: The present invention provides a method and apparatus for classifying faults. The method includes accessing wafer state data associated with at least one wafer processed by at least one processing tool and sensor tool trace data associated with the at least one processing tool and determining that at least one fault occurred based upon at least one of the wafer state data and the sensor tool trace data. The method also includes selecting, in response to determining that the at least one fault occurred, a subset of a plurality of faults based upon at least one of the wafer state data and the sensor tool trace data and selecting at least one fault from the subset of the plurality of faults based upon at least one of the wafer state data and the sensor tool trace data.

Abstract: A test structure includes a first plurality of lines and a second plurality of lines intersecting the first plurality of lines. The first and second pluralities of lines defining a grid having openings. A method for determining grid dimensions includes providing a wafer having a test structure comprising a plurality of intersecting lines that define a grid having openings; illuminating at least a portion of the grid with a light source; measuring light reflected from the illuminated portion of the grid to generate a reflection profile; and determining a dimension of the grid based on the reflection profile. A metrology tool is adapted to receive a wafer having a test structure comprising a plurality of intersecting lines that define a grid having openings. The metrology tool includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the grid.

Abstract: A method for polishing wafers includes polishing a process layer formed on a wafer, the process layer overlying a grating structure; illuminating at least a portion of the process layer and the grating structure; measuring light reflected from the illuminated portion of the process layer and the grating structure to generate a reflection profile; comparing the measured reflection profile to a target reflection profile having an acceptable degree of planarity; and terminating the polishing of the process layer based on the comparison of the measured reflection profile and the target reflection profile. A metrology tool adapted to measure a wafer having a grating structure and a process layer formed over the grating structure after initiation of a polishing process includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the process layer overlying the grating structure.

Abstract: The present invention is directed to several inventive methods of monitoring anneal processes performed on implant regions, and a system for accomplishing same. In one aspect, the method comprises forming a first plurality of implant regions in a semiconducting substrate, performing at least one anneal process on implant regions, performing a scatterometric measurement of at least one of the implant regions after at least a portion of the anneal process is performed to determine a profile of the implant region and determining an effectiveness of the anneal process based upon the determined profile of the implant region. In other embodiments, one or more parameters of the anneal process may be varied on subsequently processed substrates based upon the determined efficiency of the anneal process.

Abstract: The present invention is generally directed to various structures for analyzing electromigration, and methods of using same. In one illustrative embodiment, the method includes forming a grating structure above a semiconducting substrate, the grating structure being comprised of a plurality of conductive features, forcing an electrical current through at least one of the conductive features until a resistance of the conductive feature increases by a preselected amount, and performing at least one scatterometric measurement of the conductive feature to determine a critical dimension of the conductive feature.

Abstract: The present invention is generally directed to various methods of using scatterometry for analysis of electromigration. In one illustrative embodiment, the method comprises forming a grating structure above a semiconducting substrate, the grating structure being comprised of a plurality of conductive structures, forcing an electrical current through at least one of the conductive structures and performing scatterometric measurements of at least one conductive structure to detect a change in shape of at least a portion of the conductive structure. In further embodiments, the method comprises determining a susceptibility of at least one conductive structure to electromigration based upon the detected change in shape of the conductive structure.

Abstract: A test structure includes a plurality of lines and a plurality of contact openings defined in the lines. A method for determining contact opening dimensions includes providing a wafer having a test structure comprising a plurality of lines and a plurality of contact openings defined in the lines; illuminating at least a portion of the contact openings with a light source; measuring light reflected from the illuminated portion of the contact openings to generate a reflection profile; and determining a dimension of the contact openings based on the reflection profile. A metrology tool adapted to receive a wafer having a test structure comprising a plurality of lines and a plurality of contact openings defined in the lines includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the contact openings. The detector is adapted to measure light reflected from the illuminated portion of the contact openings to generate a reflection profile.

Abstract: A method of using high yielding spectra scatterometry measurements to control semiconductor manufacturing processes and systems for accomplishing same is disclosed. In one embodiment, the method comprises providing a library comprised of at least one target optical characteristic trace of a grating structure comprised of a plurality of gate stacks, the target trace corresponding to a semiconductor device having at least one desired electrical performance characteristic, providing a substrate having at least one grating structure formed thereabove, the formed grating structure comprised of a plurality of gate stacks, illuminating at least one grating structure formed above said substrate, measuring light reflected off of the grating structure formed above the substrate to generate an optical characteristic trace for the formed grating structure, and comparing the generated optical characteristic trace to the target trace.

Abstract: A method includes providing a wafer having a first grating structure and a second grating structure formed in a photoresist layer. At least a portion of the first and second grating structures is illuminated with a light source. Light reflected from the illuminated portion of the first and second grating structures is measured to generate a reflection profile. Misregistration between the first and second grating structures is determined based on the reflection profile. A processing line includes a photolithography stepper, a metrology tool, and a controller. The photolithography stepper is adapted to process wafers in accordance with an operating recipe. The metrology tool is adapted to receive a wafer processed in the stepper. The wafer has a first grating structure and a second grating structure formed in a photoresist layer. The metrology tool includes a light source, a detector, and a data processing unit.

Abstract: A method and an apparatus for detecting a necking error during semiconductor manufacturing. At least one semiconductor wafer is processed. Metrology data from the processed semiconductor wafer is acquired. Data from a reference library comprising optical data relating to a poly-silicon formation on a semiconductor wafer is accessed. The metrology data is compared to data from the reference library. A fault-detection analysis is performed in response to the comparison of the metrology data and the reference library data.

Abstract: The present invention is generally directed to various methods of correcting non-linearity in metrology tools, and a system for performing same. In one illustrative embodiment, the method comprises creating a non-linear model of measurement data produced by a metrology tool when measuring a plurality of features, each of which has a different, known feature size, measuring a production feature using the metrology tool to produce metrology data for the production feature, determining a correction factor to be applied to the metrology data for the production feature by comparing the non-linear model to a linear model, and applying the determined correction factor to the metrology data for the production feature.

Abstract: The present invention provides for a method and an apparatus for overlay measurements using optical techniques. At least one semiconductor device is processed. Metrology data from the processed semiconductor device is acquired. A scatterometry overlay analysis based upon the metrology data is performed. At least one modified manufacturing parameter is calculated based upon the scatterometry overlay analysis.

Abstract: The present invention is generally directed to a method of using scatterometry measurements to control the photoresist etch process. In one embodiment, the method comprises forming at least one grating structure in a layer of photoresist material, the grating structure being comprised of a plurality of photoresist features of a first size, and performing an etching process on the photoresist features of the grating structure to reduce the photoresist features to a second size that is less than the first size.

Abstract: The present invention is directed to several inventive methods for characterizing implant profiles. In one embodiment, the method comprises providing a semiconducting substrate, forming a first plurality of implant regions in the substrate, and illuminating at least one of the first plurality of implant regions with a light source in a scatterometry tool, wherein the scatterometry tool generates a profile trace corresponding to an implant profile of the illuminated implant region. The method further comprises creating at least one profile trace corresponding,to an anticipated profile of the implant region, wherein, in creating the profile trace, values of at least one of an index of refraction (n) and a dielectric constant (k) are varied, and comparing the generated profile trace to at least one created profile trace.

Abstract: A method and an apparatus for detecting a necking error during semiconductor manufacturing. At least one semiconductor wafer is processed. Metrology data from the processed semiconductor wafer is acquired. Data from a reference library comprising optical data relating to a poly-silicon formation on a semiconductor wafer is accessed. The metrology data is compared to data from the reference library. A fault-detection analysis is performed in response to the comparison of the metrology data and the reference library data.

Abstract: A test structure includes a plurality of trenches and a plurality of columns defined in the trenches. A method for determining column dimensions includes providing a wafer having a test structure comprising a plurality of trenches and a plurality of columns defined in the trenches; illuminating at least a portion of the columns with a light source; measuring light reflected from the illuminated portion of the columns to generate a reflection profile; and determining a dimension of the columns based on the reflection profile. A metrology tool adapted to receive a wafer having a test structure comprising a plurality of trenches and a plurality of columns defined in the trenches includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the columns. The detector is adapted to measure light reflected from the illuminated portion of the columns to generate a reflection profile.

Abstract: The present invention is generally directed to various methods of detecting degradation in photolithography processes based upon scatterometric measurements of grating structures, and a device comprising such structures. In one embodiment, the method comprises providing a wafer comprised of a plurality of grating structures, each of the grating structures being comprised of a plurality of features, each of the grating structures having a different critical dimension, illuminating at least one of the grating structures, measuring light reflected off of at least one of the grating structures to generate an optical characteristic trace for the grating structure, and determining the presence of residual photoresist material between the features of the grating structure by comparing the generated optical characteristic trace to at least one optical characteristic trace from a library. In some embodiments, the grating structures are arranged in a linear array.

Abstract: A method and an apparatus for performing trench depth analysis in semiconductor device manufacturing. A first processing on at least one semiconductor wafer is performed. Optical trench data is acquired from the processed semiconductor wafer. An optical trench analysis, based upon the optical trench data, is performed. A corrective feedback step is performed during a second processing of the semiconductor wafer in response to the optical trench analysis.

Abstract: A method and an apparatus for performing process lifetime tracking of trench feature using optical analysis. A plurality of process steps is performed on a first set of semiconductor wafers. A manufacturing lifetime tracking of trench features is performed. A feedback corrective process is performed on a second set of semiconductor wafers based upon the lifetime tracking trench features. A feed-forward corrective process is performed on the first set of semiconductor wafers based upon the manufacturing lifetime tracking of trench features.

Abstract: A method and an apparatus for performing periodic correction of metrology data. At least one semiconductor wafer is processed. Metrology data from the processed semiconductor wafer is acquired. At least one test wafer is processed. Test wafer metrology data from the processed test wafer is acquired. A test wafer metrology calibration process is performed upon the acquired metrology data using the acquired test wafer metrology data to produce a calibrated metrology data.