Abstract: A novel buffer design including a differential driver circuit provides an improved overall performance to a microprocessor by reducing the number of cycles required by the microprocessor to access data from a cache memory during a split cache line access. In one embodiment of the present invention, when a request to access data from a cache memory comes from a microprocessor, during a first cycle, a first sense amplifier coupled to the cache memory senses a first cache line from the cache memory. Then a first input driver circuit coupled to the first sense amplifier receives the sensed first cache line and stores the first cache line in a split buffer. Then the first sense amplifier senses a second cache line from the cache memory. Then a second sense amplifier coupled to the split buffer senses the stored first cache line from the split buffer.

Abstract: According to one embodiment, a memory cell is disclosed. The memory cell includes a first PMOS transistor, a first NMOS transistor coupled to the first PMOS transistor, a second PMOS transistor and a second NMOS transistor coupled to the first PMOS transistor. The first and second PMOS transistors receiving a bias control signal.

Abstract: According to one embodiment, a memory cell is disclosed. The memory cell includes a first PMOS transistor, a first NMOS transistor coupled to the first PMOS transistor, a second PMOS transistor and a second NMOS transistor coupled to the first PMOS transistor. The first and second PMOS transistors receiving a bias control signal.

Abstract: Multi-hit errors in a processor cache are detected by a multi-hit detection circuit coupled to the hit lines of the cache. The multi-hit detection circuit compares pairs of hit signals on the hit lines to determine if any two hit signals both indicate a hit. If multiple hits are detected, an error flag indicating the occurrence of multiple hits is generated.

Abstract: An apparatus and method are provided for powering a chip having at least one transistor. A voltage regulating device may apply a first voltage and a second voltage to the transistor. The voltage regulating device may include a mechanism to apply a third voltage to a body contact of the transistor while applying the first voltage to the transistor. This places the transistor in a reverse body bias mode which conserves energy by reducing leakage current.

Abstract: According to one embodiment, a memory cell is disclosed. The memory cell includes a first PMOS transistor, a first NMOS transistor coupled to the first PMOS transistor, a second PMOS transistor and a second NMOS transistor coupled to the first PMOS transistor. The first and second PMOS transistors receiving a bias control signal.

Abstract: Multi-hit errors in a processor cache are detected by a multi-hit detection circuit coupled to the hit lines of the cache. The multi-hit detection circuit compares pairs of hit signals on the hit lines to determine if any two hit signals both indicate a hit. If multiple hits are detected, an error flag indicating the occurrence of multiple hits is generated.

Abstract: According to one embodiment, an integrated circuit is disclosed. The integrated circuit includes a plurality of circuit blocks. Each circuit block includes a voltage differentiator that generates a local supply for the circuit block.

Abstract: According to one embodiment, an integrated circuit is disclosed. The integrated circuit includes a plurality of circuit blocks. Each circuit block includes a voltage differentiator that generates a local supply for the circuit block.

Abstract: In accordance with an embodiment of the present invention, a processor may receive a supply voltage provided by an external voltage regulator. The processor may include a voltage sensor, the output of which may be a control signal to indicate if the supply voltage is above or below a target value. This target value may be adjusted by the processor in accordance with a power management policy. The control signal may be provided to the external voltage regulator to adjust the supply voltage accordingly.

Abstract: For one embodiment of the present invention, a processor may include one or more integrated voltage regulators powered by an external voltage regulator and generating one or more local supply voltages for the processor. The one or more local supply voltages may be set to allow one or more circuits powered by the local supply voltage(s) to meet a timing requirement. The local supply voltage(s) may be adjusted by the processor in accordance with a power management policy.

Abstract: For one embodiment of the present invention, a processor may include one or more integrated voltage regulators powered by an external voltage regulator and generating one or more local supply voltages for the processor. The one or more local supply voltages may be set to allow one or more circuits powered by the local supply voltage(s) to meet a timing requirement. The local supply voltage(s) may be adjusted by the processor in accordance with a power management policy.

Abstract: According to one embodiment, a memory cell is disclosed. The memory cell includes a first PMOS transistor, a first NMOS transistor coupled to the first PMOS transistor, a second PMOS transistor and a second NMOS transistor coupled to the first PMOS transistor. The first and second PMOS transistors receiving a bias control signal.

Abstract: An apparatus and method are provided for powering a chip having at least one transistor. A voltage regulating device may apply a first voltage and a second voltage to the transistor. The voltage regulating device may include a mechanism to apply a third voltage to a body contact of the transistor while applying the first voltage to the transistor. This places the transistor in a reverse body bias mode which conserves energy by reducing leakage current.

Abstract: A method and apparatus are provided for reducing leakage current in a chip. This may include determining whether a functional block is in an inactive state and reducing the leakage current of the functional block when the functional block is in the inactive state. This may involve using a sleeping transistor or applying reverse body bias to a substrate associated with the functional block.

Abstract: A method and apparatus uses possible wordline subsequence identifiers to multiplex columns for addresses received in redundant form, including addresses received from a bypass circuit. A cache wordline decoder uses carry-nonpropagative pre-decode circuitry to identify possible subsequences from redundant addresses. Identified subsequences are combined to identify wordline sequences and to activate corresponding wordline enable signals to access data stored in cache memory. A wordline may correspond to storage locations for multiple addresses. Identified possible subsequences are used to directly multiplex cache columns and the columns are organized so as to guarantee mutual exclusivity.

Abstract: A method and apparatus are provided for reducing leakage current in a chip. This may include determining whether a functional block is in an inactive state and reducing the leakage current of the functional block when the functional block is in the inactive state. This may involve using a sleeping transistor or applying reverse body bias to a substrate associated with the functional block.

Abstract: An apparatus and method are provided for powering a chip having at least one transistor. A voltage regulating device may apply a first voltage and a second voltage to the transistor. The voltage regulating device may include a mechanism to apply a third voltage to a body contact of the transistor while applying the first voltage to the transistor. This places the transistor in a reverse body bias mode which conserves energy by reducing leakage current.

Abstract: A sense amplifier includes a pair of differential input terminals and a pair of differential output terminals. Each of a pair of precharge circuits connects a respective one of the differential output terminals to precharge potential and has a clocking input. The precharge circuits maintains the respective differential output terminals at ground in response to a precharge state of a signal at the clocking input. The sense amplifier also may include a pair of evaluation circuits, each connecting a respective one of the differential output terminals to an evaluation potential and coupled to a respective one of the differential input terminals. The evaluation circuits may transition the respective output terminal to an evaluation voltage in response to an evaluation state of a signal at the respective differential input terminal.

Abstract: A multi-level, low voltage swing memory sensing scheme. According to one aspect, low voltage swing local bitlines are provided to indicate data stored in a corresponding block of memory. The low voltage swing local bitlines are sensed on a transition of a first clock signal. Low voltage swing global bitlines indicate data sensed from the local bitlines and are sensed on a transition of a second clock signal.