Abstract: A device to sense changes in current level almost instantaneously and convert those current levels, almost instantaneously, into voltage levels that may be used by a microprocessor for logical and mathematical operations. This device employs a current conveyer to receive two inputs representing current levels. Once a sufficient difference in current levels is detected by the current conveyer, the current from each input is passed to a P-sense amplifier that converts the current to an equivalent voltage level and amplifies that voltage level.

Abstract: A device to sense changes in current level almost instantaneously and convert those current levels, almost instantaneously, into voltage levels that may be used by a microprocessor for logical and mathematical operations. This device employs a current conveyer to receive two inputs representing current levels. Once a sufficient difference in current levels is detected by the current conveyer, the current from each input is passed to a P-sense amplifier that converts the current to an equivalent voltage level and amplifies that voltage level. Thereafter, two outputs are generated reflecting an amplified voltage of the current input.

Abstract: A sense amplifier includes a pair of differential input terminals and a pair of differential output terminals. Each of a pair of precharge circuits connects a respective one of the differential output terminals to precharge potential and has a clocking input. The precharge circuits maintains the respective differential output terminals at ground in response to a precharge state of a signal at the clocking input. The sense amplifier also may include a pair of evaluation circuits, each connecting a respective one of the differential output terminals to an evaluation potential and coupled to a respective one of the differential input terminals. The evaluation circuits may transition the respective output terminal to an evaluation voltage in response to an evaluation state of a signal at the respective differential input terminal.

Abstract: A method for evaluating the robustness of a logic circuit to soft errors involves injecting a current pulse into a node of the logic circuit. The current pulse is shaped to be representative of a high-energy particle strike, and may have an amplitude that is sufficient to momentarily discharge an output node of the logic circuit. The output node of the logic circuit is electrically monitored to determine whether a transition occurs from a first logic state to a second logic state in response to the injected current pulse. In the case where the state of the output node does flip in response to the injected current pulse, a waveform of the injected current pulse is integrated over time to compute a critical charge level (QCRIT). Where the amplitude is insufficient to cause the output node to flip, the amplitude of the injected current pulse is incremented and the above steps are repeated using the incremented amplitude until a logic state transition does occur at the output node.

Abstract: A memory. For one aspect, the memory comprises memory cells that are arranged in columns. The memory also includes a global bitline that is shared by at least two of the columns of memory cells. During a memory read operation, the global bitline is responsive to data stored in one or more of the at least two columns of memory if either of the at least two columns of memory is to be read from.

Abstract: A sense amplifier may include a pair of output terminals, an evaluation circuit, a reference circuit and a pair of clamping circuits. The evaluation circuit connects a first output terminal to an evaluation potential. It receives a data signal at an input terminal. The reference circuit connects a second output terminal to the evaluation potential. The reference circuit receives a pair of reference signals on other input terminals. The clamping circuits each couple a respective one of the output terminals to a precharge potential. Inputs of each clamping circuit are coupled to the other of the output terminals.

Abstract: In an automated method of sizing data transistors for a symmetrical differential sense amplifier that includes a pair of input terminals, a pair of output terminals, a pair of data transistors each having a gate coupled to a respective input terminal, and a pair of loading transistors each coupled to a respective output terminal and to a respective data transistor and having a gate coupled to the other output terminal: expected manufacturing variations of circuit parameters are determined based upon an initial size of the data transistors, an offset potential is calculated therefrom that will cause the sense amplifier to evaluate and, if the calculated offset potential exceeds an expected threshold potential for the sense amplifier, the data transistors are resized, expected manufacturing variations of circuit parameters are determined based on the resized data transistors and the calculating step is repeated.

Abstract: In one embodiment, a memory cell having a first port and a second port is provided. A first word line is associated with the first port, and a second word line is associated with the second port. A first driver is associated with the first word line, and a second driver is associated with the second word line. A decoder is associated with the first and second drivers.

Abstract: In one embodiment, an apparatus including an asymmetrical memory cell having a first inverter and a second inverter is provided. The first inverter is larger than said second inverter.

Abstract: A CMOS logic circuit comprises a logic gate having an input node (e.g., a storage node) coupled to a positive supply potential through a p-type field-effect transistor (PFET), with one or more n-type field-effect transistors (NFETs) being coupled between the storage node and a negative supply potential. Since the response of the circuit to a high-energy particle strike is dominated by the N+ diffusion associated with the NFETs when the state of the storage node is high, i.e., a logical "1", the gate has a switching point that is set closer to the negative supply potential than to the positive supply potential.

Abstract: A multi-way, set-associative cache utilizes a single ECC code in which the ECC bits are evenly distributed among the tag arrays to protect all of the multi-way tags. The cache includes a plurality of data arrays--one for each way of the cache--along with a corresponding plurality of tag arrays. The ECC bits are appended to each tag entry for one of the multiple ways. A single ECC logic block is shared by the tag arrays to detect tag errors. Additional comparator logic is coupled to the tag arrays to perform tag matching.

Abstract: A CMOS latch circuit comprises a data input node, an output node, and first and second inverters, each of which have an input coupled to the data input node, and an output coupled to the output node. Pairs of feedback NFETs and PFETs are each coupled in series between V.sub.CC and ground. Intermediate nodes between each of the NFET and PFET feedback pairs are coupled to the data input node. The gate of the first feedback NFET is coupled to the data input node, and the gate of the second NFET is coupled to the output node. Similarly, the gate of the first PFET is coupled to the output node, and the gate of the second PFET is coupled to the data input node. The CMOS latch circuit maintains a logic state at the output node regardless of a high-energy particle strike.

Abstract: A static random-access memory (SRAM) cell with one or more storage elements connected to a sensing component by a single transmission line. Each storage element is connected to the transmission line through a switch so that one storage element at a time can be actively connected to the transmission line. The sensing component produces an output indicating the value stored in the active storage element then switched onto the transmission line.