Abstract: A thin film interleaver device is disclosed. The thin film interleaver includes thin film optics. The thin film(s) are formed such that they reflect one group of wavelengths while allowing a second group of wavelengths to pass through the thin film(s). The thin film(s) exhibit a flat top frequency response across the channel bandwidths of the multiplexed signal for which the thin film filter is designed such that the thin film interleaver is less sensitive to wavelength drift and temperature variations.

Abstract: For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.

Abstract: In embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS pull-up devices are effectively strengthened by forward biasing the PMOS n-wells or by utilizing a lower threshold voltage PMOS device by implanting a lower halo dose in the PMOS device. In WRITE mode of a column, the two PMOS pull-up devices are effectively weakened by reverse biasing the PMOS n-wells or by coupling the sources of the NMOS devices to virtual ground (VSSi).

Abstract: In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.

Abstract: In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.

Abstract: A dynamic multi-voltage memory array features SRAM cells that are subjected to different biasing conditions, depending on the operating mode of the cells. The selected SRAM cell receives a first voltage when a read operation is performed, and receives a second voltage when a write operation is performed. By biasing the cell differently for the two distinct operations, a total decoupling of the read and write operations is achieved. The disclosed memory array, as well as future SRAM designs incorporating the multi-voltage capability thus avoid the conflicting requirements of read and write operations. Random single-bit failures of the memory array are reduced, due to the improvement in read stability and write margin.

Abstract: A dynamic multi-voltage memory array features SRAM cells that are subjected to different biasing conditions, depending on the operating mode of the cells. The selected SRAM cell receives a first voltage when a read operation is performed, and receives a second voltage when a write operation is performed. By biasing the cell differently for the two distinct operations, a total decoupling of the read and write operations is achieved. The disclosed memory array, as well as future SRAM designs incorporating the multi-voltage capability thus avoid the conflicting requirements of read and write operations. Random single-bit failures of the memory array are reduced, due to the improvement in read stability and write margin.

Abstract: This disclosure concerns low insertion loss optical circulators. In one example, the optical circulator has four ports and includes a polarization dividing and combining element that is positioned adjacent the first and fourth ports and is adapted to divide a beam of light into two beams of light of orthogonal polarizations. The polarization dividing and combining element is also adapted to combine two beams of light of orthogonal polarizations into one beam of light. The optical circulator also includes a Faraday rotator positioned near the second port, and a Faraday rotator positioned near the third port. The Faraday rotator rotates beams of light before or after the pass through the polarization dividing and combining elements.

Abstract: A package for maintaining alignment of components includes a frame and a beam with the beam attached to the frame and one end of the beam. One or more components are mounted to the beam. The frame and a portion of the beam are separated from each other by a channel which allows portions of the beam to flex substantially independently of the frame when a force is applied to the frame. Thus, the effects resulting from forces applied to the frame are not experienced by the beam, or are at least attenuated, so that the alignment of the components mounted on the beam is substantially preserved.

Abstract: In embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS pull-up devices are effectively strengthened by forward biasing the PMOS n-wells or by utilizing a lower threshold voltage PMOS device by implanting a lower halo dose in the PMOS device. In WRITE mode of a column, the two PMOS pull-up devices are effectively weakened by reverse biasing the PMOS n-wells or by coupling the sources of the NMOS devices to virtual ground (VSSi).

Abstract: A method and apparatus for a four transistor SRAM comprising an array or block of cells. Each cell comprises a pair of pass transistors and a pair of pull-down transistors. In one embodiment of the invention, when the SRAM block is in a standby mode, the difference between the voltage at the gate and the voltage at the source of each pass transistor is greater than 0, and less than the threshold voltage of the pass transistor. In one embodiment of the invention a ground connection of the memory cell is switched such that when the SRAM block is in the standby mode, the ground connection is a virtual ground connection and when the SRAM block is in an active mode the ground connection is a global ground connection.

Abstract: Methods and apparatus for tuning an optical element include, in one aspect, an optical element having a specified response at a predetermined location and means for redirecting incident light to a location on the optical element other than the predetermined location so as to achieve a desired response.

Abstract: A method and apparatus for a four transistor SRAM comprising an array or block of cells. Each cell comprises a pair of pass transistors and a pair of pull-down transistors. In one embodiment of the invention, when the SRAM block is in a standby mode, the difference between the voltage at the gate and the voltage at the source of each pass transistor is greater than 0, and less than the threshold voltage of the pass transistor. In one embodiment of the invention a ground connection of the memory cell is switched such that when the SRAM block is in the standby mode, the ground connection is a virtual ground connection and when the SRAM block is in an active mode the ground connection is a global ground connection.

Abstract: An optical interleaver for use in a range of telecommunications applications including optical multiplexers/demultiplexers and optical routers. The optical device includes an optical processing loop which allows multi-stage performance characteristics to be achieved with a single physical filtration stage. Optical processing on the first leg and second legs of the loop is asymmetrical thereby improving the integrity of the optical signals by effecting complementary chromatic dispersion on the first and second legs. A fundamental filter cell within the interleaver filters optical signals propagating on each of the two legs of the optical loop which intersects the fundamental filter cell.

Abstract: An optical device that can be used in a range of telecommunications applications including optical multiplexers/demultiplexers and optical routers. The optical device includes an optical processing loop which allows multi-stage performance characteristics to be achieved with a single physical filtration stage. Optical processing on the first leg and second legs of the loop is asymmetrical thereby improving the integrity of the optical signals by effecting complementary chromatic dispersion on the first and second legs. In an embodiment of the invention the optical device includes a fundamental filter cell, a retro reflector and a splitter/combiner. The fundamental filter cell filters optical signals propagating on each of two legs of an optical loop which intersects the fundamental filter cell.

Abstract: An optical add/drop patch cord. The optical add/drop patch cord has an optical add/drop component enclosed by a casing. An input fiber is optically coupled to the optical add/drop component and permanently or detachably connected to the casing. A drop fiber is optically coupled to the optical add/drop component and permanently or detachably connected to the casing. An add fiber is optically coupled to the optical add/drop component and permanently connected to the casing. An output fiber is optically coupled to the optical add/drop component and permanently connected to the casing.

Abstract: A batched process for producing optical components for use in fiber-optic networks. The process involves creating optical substrate blocks with thin-film filters on at least one surface of the of the substrate blocks. Other surfaces on the blocks are finely polished such the several blocks may be fused together at the polished surfaces. By placing the blocks such that the thin-film filters on adjacent blocks are diagonally opposed and then fusing together adjacent blocks, the blocks connected in this manner can perform various optical functions. Some of the optical components that can be formed using this process include power taps, optical add/drop modules, multiplexers, and demultiplexers.

Abstract: A method and apparatus for a four transistor SRAM comprising an array or block of cells. Each cell comprises a pair of pass transistors and a pair of pull-down transistors. In one embodiment of the invention, when the SRAM block is in a standby mode, the difference between the voltage at the gate and the voltage at the source of each pass transistor is greater than 0, and less than the threshold voltage of the pass transistor. In one embodiment of the invention a ground connection of the memory cell is switched such that when the SRAM block is in the standby mode, the ground connection is a virtual ground connection and when the SRAM block is in an active mode the ground connection is a global ground connection.

Abstract: A memory and method for accessing data in a memory which uses non redundant-form address decoders is disclosed. Lines in subarrays of the memory are selected using the redundant-form addresses. The least significant bit of the non redundant-form address is used to select between these lines. The compare function of the cache memory is then done with a non redundant-form address.

Abstract: An optical device that can be used in a range of telecommunications applications including optical multiplexers/demultiplexers and optical routers. The optical device includes an optical processing loop which allows multi-stage performance characteristics to be achieved with a single physical filtration stage. Optical processing on the first leg and second legs of the loop is asymmetrical thereby improving the integrity of the optical signals by effecting complementary chromatic dispersion on the first and second legs. In an embodiment of the invention the optical device includes a fundamental filter cell, a retro reflector and a splitter/combiner. The fundamental filter cell filters optical signals propagating on each of two legs of an optical loop which intersects the fundamental filter cell.