Abstract: A shared error correcting circuit reduces memory overhead by sharing a fixed number of ECC bits among two or more memory units in a semiconductor memory. A single ECC block is used to generate check bits and syndrome bits. The ECC block tests each of the memory units by using the total number of ECC bits available in the ECC cells. Thus, the memory overhead is reduced from that in standard ECC designs.

Abstract: A portion of an optical device is disclosed. In one aspect of the present invention, the device comprises a cylinder formed about an axis having first and second ends, the second end being formed so as to define a segment of an inward-facing concave spherical surface. A module is provided defining a cylinder formed about the axis and having first and second ends and an optical element disposed therein about the axis. The first end of the module is formed so as to define a segment of an outward-facing convex spherical surface, and the convex surface is complimentary in shape to the concave surface. The complimentary concave and convex surfaces of the cylinder and the module are mated so as to allow the optical element to be aligned about a plane forming a predetermined angle with the axis.

Abstract: Various embodiments of methods and systems of using TEC (Thermal-Diffusion Expanded Core) optical fiber to increase the power handling capabilities of an optical device are disclosed. In one embodiment, an optical device includes a TEC optical fiber that includes a first core. The diameter of the first core is larger at the end of the TEC optical fiber than it is in the unexpanded portion of the TEC optical fiber. The optical device also includes a focusing lens configured to focus light into the end of the TEC optical fiber so that a light spot created by the focused light on a surface of the end of the TEC optical fiber has a light spot diameter that is larger than the diameter of the first core in the unexpanded portion of the TEC optical fiber.

Abstract: The present invention generally relates to fiber optical systems having mismatched mode field diameters. In order to reduce mode mismatched insertion loss in a system requiring coupling among fibers with mismatched mode field diameters, the core at the termination of each of the fibers having a mode field diameter (MFD) smaller than the largest mode field diameter in the system is thermally expanded to provide a MFD at the termination which matches the largest MFD. Embodiments of the invention include a novel pump signal combiner for fiber amplifiers.

Abstract: A memory and method for accessing data in a memory which uses non redundant-form address decoders is disclosed. Lines in subarrays of the memory are selected using the redundant-form addresses. The least significant bit of the non redundant-form address is used to selected between these lines. The compare function of the cache memory is then done with a non redundant-form address.

Abstract: A cache access system is provided. The cache access system includes a plurality of ways coupled to decoders. Each decoder is to find a data location in one way based on an address. The cache access system also includes a tag unit to compare the address with a tag array and to generate a hit/miss signal. Sense amplifiers are coupled to each of the ways, wherein one of said sense amplifiers is to read data from the data location if it receives said hit/miss signal as a hit.

Abstract: A static random-access memory (SRAM) comprises multi-port storage cells with built-in column-interleave selection circuitry which allow a storage cell to be written to via a plurality of different write paths. Column selects are built into each storage cell by adding an additional isolating switch between the storage node of the storage cell and the bitline of a particular write path in order to prevent a cell write from affecting other storage cells connected to the same wordline in the same interleaved array. The write data bus corresponding to each write path for all interleaved cells are shared by all storage cells in a common interleave group, and each adjacent pair of storage cells in a common row share bitlines coupled to the common data bus, resulting in smaller number of required bitlines.

Abstract: In some embodiments, the invention includes an integrated circuit including a bitline and a bitline#, wordlines, and memory cells. The memory cells each corresponding to one of the wordlines and each include first and second pass transistors coupled between first and second storage nodes, respectively, and the bitline and bitline#, respectively, the corresponding wordline being coupled to gates of the first and second pass transistors. The memory cells include first and second inverters cross-coupled between the first and second storage nodes, wherein the first and second pass transistors each have a lower threshold voltage than do transistors of the first and second inverters. Wordline voltage control circuitry coupled to the wordlines selectively controls wordline signals on the wordlines.

Abstract: A single-ended SRAM cell design reduces SRAM size and provides high storage cell noise margin. A virtual ground line is coupled to the source of the driver NFET of each I/O port inverter of each storage cell in a common bitline column. An isolation mechanism couples the virtual ground line to a low reference voltage during reads and during a write of a "0" to a storage cell, and isolates the virtual ground line from the low reference voltage during a write of a "1" to a storage cell. A clamping device is coupled to the virtual ground line to prevent the potential on the virtual ground line from exceeding the threshold voltage of the isolation mechanism and flipping the stored value in any of the other commonly coupled storage cells when a "1" is being written to another of the commonly coupled storage cells.

Abstract: An asymmetric sense amplifier is disclosed for use with single-ended memory arrays. The sense amplifier has a bit input, a reference input, an enable input, and bistable output circuitry. The reference input may simply be tied to V.sub.DD. The bistable output circuitry includes first and second output nodes disposed between first and second pull-up/pull-down paths, respectively. The first pull-up and pull-down paths may include first pull-up and pull-down FET channels, respectively. The second pull-up and pull-down paths may include second pull-up and pull-down FET channels, respectively. The bistable output circuitry is operable to be stable in first and second states. In both states, the output nodes are at opposite potentials. The sense amplifier is asymmetrical in the following sense: Either the second pull-down FET channel is wider than the first pull-down FET channel, or the first pull-up FET channel is wider than the second pull-up FET channel, or both.