Patents by Inventor Ki-Jun Sung

Ki-Jun Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240030192
    Abstract: A stack package, and a method of manufacturing the same, includes a first encapsulant layer formed on a carrier. Also semiconductor dies are sequentially offset stacked on the first encapsulant layer. Vertical connectors connected to the semiconductor dies are formed. A second encapsulant layer coupled to the first encapsulant layer is formed to encapsulate the vertical connectors and the semiconductor dies. Redistribution layers connected to the vertical connectors are formed on the second encapsulant layer.
    Type: Application
    Filed: October 2, 2023
    Publication date: January 25, 2024
    Applicant: SK hynix Inc.
    Inventors: Ki Jun SUNG, Chae Sung LEE
  • Patent number: 11804474
    Abstract: A stack package, and a method of manufacturing the same, includes a first encapsulant layer formed on a carrier. Also semiconductor dies are sequentially offset stacked on the first encapsulant layer. Vertical connectors connected to the semiconductor dies are formed. A second encapsulant layer coupled to the first encapsulant layer is formed to encapsulate the vertical connectors and the semiconductor dies. Redistribution layers connected to the vertical connectors are formed on the second encapsulant layer.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: October 31, 2023
    Assignee: SK hynix Inc.
    Inventors: Ki Jun Sung, Chae Sung Lee
  • Patent number: 11495545
    Abstract: A semiconductor package includes an outer redistributed line (RDL) structure, a first semiconductor chip disposed on the outer RDL structure, a stack module stacked on the first semiconductor chip, and a bridge die stacked on the outer RDL structure. A portion of the stack module laterally protrudes from a side surface of the first semiconductor chip. The bridge die supports the protruding portion of the stack module. The stack module includes an inner RDL structure, a second semiconductor chip disposed on the inner RDL structure, a capacitor die disposed on the inner RDL structure, and an inner encapsulant. The capacitor die acts as a decoupling capacitor of the second semiconductor chip.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: November 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Jong Hoon Kim, Ki Jun Sung, Ki Bum Kim
  • Publication number: 20220293564
    Abstract: A stack package, and a method of manufacturing the same, includes a first encapsulant layer formed on a carrier. Also semiconductor dies are sequentially offset stacked on the first encapsulant layer. Vertical connectors connected to the semiconductor dies are formed. A second encapsulant layer coupled to the first encapsulant layer is formed to encapsulate the vertical connectors and the semiconductor dies. Redistribution layers connected to the vertical connectors are formed on the second encapsulant layer.
    Type: Application
    Filed: September 8, 2021
    Publication date: September 15, 2022
    Applicant: SK hynix Inc.
    Inventors: Ki Jun SUNG, Chae Sung LEE
  • Patent number: 11444063
    Abstract: A semiconductor package may include: at least one semiconductor chip disposed such that an active surface on which a plurality of chip pads are disposed faces a redistribution conductive layer; a plurality of vertical interconnectors, each with one end connected to a respective chip pad, extending in a vertical direction toward the redistribution conductive layer; a molding layer covering the semiconductor chip and the vertical interconnectors while exposing an other end of each of the vertical interconnectors that is not connected to the chip pad; a plurality of landing pads disposed over the molding layer, and each connected to the other end of each of the vertical interconnectors; a redistribution insulating layer covering the molding layer with an opening that collectively exposes the landing pads; and the redistribution conductive layer that extends over the molding layer and the redistribution insulating layer while being connected to each of the landing pads.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventors: Ki Jun Sung, Chae Sung Lee
  • Publication number: 20220230994
    Abstract: A semiconductor package may include: at least one semiconductor chip disposed such that an active surface on which a plurality of chip pads are disposed faces a redistribution conductive layer; a plurality of vertical interconnectors, each with one end connected to a respective chip pad, extending in a vertical direction toward the redistribution conductive layer; a molding layer covering the semiconductor chip and the vertical interconnectors while exposing an other end of each of the vertical interconnectors that is not connected to the chip pad; a plurality of landing pads disposed over the molding layer, and each connected to the other end of each of the vertical interconnectors; a redistribution insulating layer covering the molding layer with an opening that collectively exposes the landing pads; and the redistribution conductive layer that extends over the molding layer and the redistribution insulating layer while being connected to each of the landing pads.
    Type: Application
    Filed: May 5, 2021
    Publication date: July 21, 2022
    Applicant: SK hynix Inc.
    Inventors: Ki Jun SUNG, Chae Sung LEE
  • Patent number: 11322446
    Abstract: A system-in-package includes a redistributed line (RDL) structure, a first semiconductor chip, a second semiconductor chip, and a bridge die. The RDL structure includes a first RDL pattern to which a first chip pad of the first semiconductor chip is electrically connected. The second semiconductor chip is stacked on the first semiconductor chip such that the second semiconductor chip protrudes past a side surface of the first semiconductor chip, wherein a second chip pad disposed on the protrusion is electrically connected to the first RDL pattern through the bridge die.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventors: Jong Hoon Kim, Ki Jun Sung, Ki Bum Kim
  • Patent number: 11127296
    Abstract: An apparatus and a method for inducing safe driving of a surrounding vehicle are applied to a vehicle parked on a road and may identify an object (surrounding vehicle, pedestrian) based on an image obtained by a camera photographing an approaching object. The apparatus and method blink a lamp of the parked vehicle according to the identified object, thus preventing a traffic accident occurring due to the parked vehicle. The apparatus includes: a plurality of lamps mounted on an external portion of the parked vehicle; a camera provided in the parked vehicle and configured to photograph a surrounding image; and a controller configured to identify an object approaching the parked vehicle in the surrounding image photographed by the camera and blink at least one lamp according to the identified object.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: September 21, 2021
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventor: Ki Jun Sung
  • Patent number: 10985106
    Abstract: A stack package includes a plurality of sub-packages vertically stacked. Each of the sub-packages includes a bridge die having a plurality of vertical interconnectors and a semiconductor die. A first group of vertical interconnectors disposed in a first bridge die included in a first sub-package of the sub-packages and other vertical interconnectors connected to the first group of vertical interconnectors constitute a first electric path, and a second group of vertical interconnectors disposed in a second bridge die included in a second sub-package of the sub-packages and other vertical interconnectors connected to the second group of vertical interconnectors constitute a second electric path. The first and second electric paths are electrically isolated from each other and disposed to provide two separate electric paths.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 20, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Jun Sung, Ha Gyeong Song
  • Patent number: 10971452
    Abstract: A semiconductor package includes a base substrate and first to Nth sub packages sequentially stacked over the base substrate with each sub package including a semiconductor die and a bridge die disposed on at least one side of the semiconductor die and electrically connected to the semiconductor die, where N is a natural number equal to or more than two (2). The semiconductor package also includes a molding layer formed on the base substrate and exposing an Nth conductive post included in the Nth sub package while covering the first to Nth sub packages. The semiconductor package further includes a shielding layer formed on the molding layer and electrically connected to the Nth conductive post.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventor: Ki-Jun Sung
  • Publication number: 20210074641
    Abstract: A semiconductor package includes a base substrate and first to Nth sub packages sequentially stacked over the base substrate with each sub package including a semiconductor die and a bridge die disposed on at least one side of the semiconductor die and electrically connected to the semiconductor die, where N is a natural number equal to or more than two (2). The semiconductor package also includes a molding layer formed on the base substrate and exposing an Nth conductive post included in the Nth sub package while covering the first to Nth sub packages. The semiconductor package further includes a shielding layer formed on the molding layer and electrically connected to the Nth conductive post.
    Type: Application
    Filed: January 27, 2020
    Publication date: March 11, 2021
    Applicant: SK hynix Inc.
    Inventor: Ki-Jun SUNG
  • Publication number: 20210056851
    Abstract: An apparatus and a method for inducing safe driving of a surrounding vehicle are applied to a vehicle parked on a road and may identify an object (surrounding vehicle, pedestrian) based on an image obtained by a camera photographing an approaching object. The apparatus and method blink a lamp of the parked vehicle according to the identified object, thus preventing a traffic accident occurring due to the parked vehicle. The apparatus includes: a plurality of lamps mounted on an external portion of the parked vehicle; a camera provided in the parked vehicle and configured to photograph a surrounding image; and a controller configured to identify an object approaching the parked vehicle in the surrounding image photographed by the camera and blink at least one lamp according to the identified object.
    Type: Application
    Filed: March 11, 2020
    Publication date: February 25, 2021
    Applicants: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventor: Ki Jun Sung
  • Patent number: 10903196
    Abstract: A semiconductor package includes first and second semiconductor dies, first and second redistributed line structures, a first bridge die, and a vertical connector. The first semiconductor die and the first bridge die are disposed on the first redistributed line structure. The first bridge die is disposed to provide a level difference between the first semiconductor die and the first bridge die, the first bridge die having a height that is less than a height of the first semiconductor die. The second redistributed line structure has a protrusion, laterally protruding from a side surface of the first semiconductor die when viewed from a plan view, and a bottom surface of the second redistributed line structure is in contact with a top surface of the first semiconductor die. The second semiconductor die is disposed on the second redistributed line structure. The vertical connector is disposed between the bridge die and the protrusion of the second redistributed line structure to support the protrusion.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: January 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Jun Sung, Sang Hyuk Lim
  • Patent number: 10903131
    Abstract: A semiconductor package includes a semiconductor die and a bridge die. The bridge die includes through vias, and the through vias are connected to post bumps. The through vias are electrically connected to the semiconductor die by redistribution lines.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: January 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Jun Sung, Sungkyu Kim
  • Patent number: 10811359
    Abstract: A stack package includes a first sub-package, a second sub-package stacked on the first sub-package. The first sub-package is configured to include first and second semiconductor dies, a first flexible bridge die disposed between the first and second semiconductor dies.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: October 20, 2020
    Assignee: Sk hynix Inc.
    Inventors: Ki Jun Sung, Kyoung Tae Eun
  • Publication number: 20200328189
    Abstract: A semiconductor package includes a second semiconductor die stacked on a first semiconductor die, an encapsulant layer on the first semiconductor die and adjacent to the second semiconductor die, and a thermal conduction network structure including a plurality of thermal conduction balls dispersed in the encapsulant layer.
    Type: Application
    Filed: November 19, 2019
    Publication date: October 15, 2020
    Applicant: SK hynix Inc.
    Inventor: Ki Jun SUNG
  • Publication number: 20200273801
    Abstract: A semiconductor package includes an outer redistributed line (RDL) structure, a first semiconductor chip disposed on the outer RDL structure, a stack module stacked on the first semiconductor chip, and a bridge die stacked on the outer RDL structure. A portion of the stack module laterally protrudes from a side surface of the first semiconductor chip. The bridge die supports the protruding portion of the stack module. The stack module includes an inner RDL structure, a second semiconductor chip disposed on the inner RDL structure, a capacitor die disposed on the inner RDL structure, and an inner encapsulant. The capacitor die acts as a decoupling capacitor of the second semiconductor chip.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 27, 2020
    Applicant: SK hynix Inc.
    Inventors: Jong Hoon KIM, Ki Jun SUNG, Ki Bum KIM
  • Publication number: 20200273800
    Abstract: A system-in-package includes a redistributed line (RDL) structure, a first semiconductor chip, a second semiconductor chip, and a bridge die. The RDL structure includes a first RDL pattern to which a first chip pad of the first semiconductor chip is electrically connected. The second semiconductor chip is stacked on the first semiconductor chip such that the second semiconductor chip protrudes past a side surface of the first semiconductor chip, wherein a second chip pad disposed on the protrusion is electrically connected to the first RDL pattern through the bridge die.
    Type: Application
    Filed: October 28, 2019
    Publication date: August 27, 2020
    Applicant: SK hynix Inc.
    Inventors: Jong Hoon KIM, Ki Jun SUNG, Ki Bum KIM
  • Publication number: 20200273799
    Abstract: A system-in-package includes a redistributed line (RDL) structure, a first semiconductor chip, a second semiconductor chip, a second sub-package, a first bridge die, and a second bridge die. The RDL structure includes a first RDL pattern to which a first chip pad of the first semiconductor chip is electrically connected. The second semiconductor is stacked on the first semiconductor chip such that the second semiconductor chip protrudes past a side surface of the first semiconductor chip, wherein a second chip pad disposed on the protrusion of the second semiconductor chip is electrically connected to the first RDL pattern through the first bridge die. The second bridge die is disposed to electrically connect the second sub-package to the first semiconductor chip.
    Type: Application
    Filed: October 28, 2019
    Publication date: August 27, 2020
    Applicant: SK hynix Inc.
    Inventors: Ki Jun SUNG, Jong Hoon KIM, Jae Min KIM
  • Publication number: 20200176385
    Abstract: A stack package includes a first sub-package, a second sub-package stacked on the first sub-package. The first sub-package is configured to include first and second semiconductor dies, a first flexible bridge die disposed between the first and second semiconductor dies.
    Type: Application
    Filed: August 6, 2019
    Publication date: June 4, 2020
    Applicant: SK hynix Inc.
    Inventors: Ki Jun SUNG, Kyoung Tae EUN