Abstract: A stack package includes a second sub-package stacked on a first sub-package. The stack package also includes a plurality of dummy balls located between the first and second sub-packages to support the second sub-package. Each of the first and second sub-packages includes a semiconductor die and a bridge, die which are spaced apart from each other.

Abstract: Semiconductor packages are provided. The semiconductor package includes a first semiconductor chip to which a first elevated pillar bump is connected, a second semiconductor chip stacked on the first semiconductor chip to leave revealed the first elevated pillar bump and configured to include a first chip pad disposed on a center region of the second semiconductor chip, a third semiconductor chip offset and stacked on the second semiconductor chip to leave revealed the first chip pad, and a chip supporter supporting an overhang of the third semiconductor chip.

Abstract: A semiconductor package includes first and second semiconductor dies, first and second redistributed line structures, a first bridge die, and a vertical connector. The first semiconductor die and the first bridge die are disposed on the first redistributed line structure. The first bridge die is disposed to provide a level difference between the first semiconductor die and the first bridge die, the first bridge die having a height that is less than a height of the first semiconductor die. The second redistributed line structure has a protrusion, laterally protruding from a side surface of the first semiconductor die when viewed from a plan view, and a bottom surface of the second redistributed line structure is in contact with a top surface of the first semiconductor die. The second semiconductor die is disposed on the second redistributed line structure. The vertical connector is disposed between the bridge die and the protrusion of the second redistributed line structure to support the protrusion.

Abstract: A stack package includes a plurality of sub-packages vertically stacked. Each of the sub-packages includes a bridge die having a plurality of vertical interconnectors and a semiconductor die. A first group of vertical interconnectors disposed in a first bridge die included in a first sub-package of the sub-packages and other vertical interconnectors connected to the first group of vertical interconnectors constitute a first electric path, and a second group of vertical interconnectors disposed in a second bridge die included in a second sub-package of the sub-packages and other vertical interconnectors connected to the second group of vertical interconnectors constitute a second electric path. The first and second electric paths are electrically isolated from each other and disposed to provide two separate electric paths.

Abstract: A stack package includes a second sub-package stacked on a first sub-package. The stack package also includes a plurality of dummy balls located between the first and second sub-packages to support the second sub-package. Each of the first and second sub-packages includes a semiconductor die and a bridge, die which are spaced apart from each other.

Abstract: A chip stack package includes first and second semiconductor chips. A first redistribution line structure is disposed on a front surface of the first semiconductor chip, and the first redistribution line structure extends onto a side surface of the first semiconductor chip. A second redistribution line structure is disposed on the front surface of the first semiconductor chip, and the second redistribution line structure extends onto the side surface of the first semiconductor chip. A third redistribution line structure is disposed on a front surface of the second semiconductor chip, and the third redistribution line structure extends onto a side surface of the second semiconductor chip to be electrically connected to the second redistribution line structure.

Abstract: A semiconductor package includes a semiconductor die and a bridge die. The bridge die includes through vias, and the through vias are connected to post bumps. The through vias are electrically connected to the semiconductor die by redistribution lines.

Abstract: A chip stack package includes first and second semiconductor chips. A first redistribution line structure is disposed on a front surface of the first semiconductor chip and the first redistribution line structure extends onto a side surface of the first semiconductor chip. A second redistribution line structure is disposed on the front surface of the first semiconductor chip, and the second redistribution line structure extends onto the side surface of the first semiconductor chip. A third redistribution line structure is disposed on a front surface of the second semiconductor chip, and the third redistribution line structure extends onto a side surface of the second semiconductor chip to be electrically connected to the second redistribution line structure.

Abstract: Semiconductor packages are provided. The semiconductor package includes a first semiconductor chip to which a first elevated pillar bump is connected, a second semiconductor chip stacked on the first semiconductor chip to leave revealed the first elevated pillar bump and configured to include a first chip pad disposed on a center region of the second semiconductor chip, a third semiconductor chip offset and stacked on the second semiconductor chip to leave revealed the first chip pad, and a chip supporter supporting an overhang of the third semiconductor chip.

Abstract: A semiconductor package may be provided. The semiconductor package may include a first semiconductor chip and a second semiconductor chip disposed on an interconnection layer. The semiconductor package may include a heat transferring block disposed between the first and second semiconductor chips to be mounted on the interconnection layer. Related methods are also provided.

Abstract: A semiconductor package may be provided. The semiconductor package may include a first semiconductor chip and a second semiconductor chip disposed on an interconnection layer. The semiconductor package may include a heat transferring block disposed between the first and second semiconductor chips to be mounted on the interconnection layer. Related methods are also provided.

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.

Abstract: There is provided a structure and a method of manufacturing a semiconductor package. The method includes disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, recessing a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, and mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

Abstract: There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device.

Abstract: There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device.

Abstract: Wafer level packages are provided. The wafer level package includes alignment marks disposed at a first surface of a protection wafer, a semiconductor die disposed on the first surface of the protection wafer to be spaced apart from the alignment marks, a first photosensitive dielectric layer covering the semiconductor die and having a flat top surface, and a second dielectric layer covering the flat top surface of the first photosensitive dielectric layer. Redistribution lines are disposed between the first photosensitive dielectric layer and the second dielectric layer and electrically connected to the semiconductor die through first opening portions penetrating the first photosensitive dielectric layer. Outer connectors are disposed on the second dielectric layer and electrically connected to the redistribution lines through second opening portions penetrating the second dielectric layer.

Abstract: There is provided a structure and a method of manufacturing a semiconductor package. The method includes disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, recessing a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, and mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

Abstract: A semiconductor package includes first bump pads on a first surface of an interconnection structure layer, elevated pads thicker than the first bump pads on the first surface of the interconnection structure layer, a first semiconductor device connected on the first bump pads, through mold ball connectors connected on the elevated pads, respectively, a molding layer disposed covering the first surface of the interconnection structure layer to expose a portion of each of the through mold ball connectors, outer connectors respectively attached to the through mold ball connectors, and a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.

Abstract: According to various embodiments, there may be provided packages, semiconductors, and wafer level packages, and there may be provided methods of manufacturing packages, semiconductors, and wafer level packages. A method of manufacturing a wafer level package may include forming alignment marks at a surface of a protection wafer, mounting semiconductor dice on the protection wafer using the alignment marks, forming a first dielectric layer covering the semiconductor dice, planarizing a top surface of the first photosensitive layer, exposuring and developing portions of the planarized first dielectric layer to form opening portions exposing portions of the semiconductor dice, and forming redistribution lines on the first photosensitive dielectric layer. A second dielectric layer may be formed to cover the redistribution lines. Related wafer level packages may also be provided.