Patents by Inventor Ki Jun Yun
Ki Jun Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240098275Abstract: A method for decoding an image based on an intra prediction, comprising: obtaining a first prediction pixel of a first region in a current block by using a neighboring pixel adjacent to the current block; obtaining a second prediction pixel of a second region in the current block by using the first prediction pixel of the first region; and decoding the current block based on the first and the second prediction pixels.Type: ApplicationFiled: November 15, 2023Publication date: March 21, 2024Inventors: Je Chang JEONG, Ki Baek KIM, Won Jin LEE, Hye Jin SHIN, Jong Sang YOO, Jang Hyeok YUN, Kyung Jun LEE, Jae Hun KIM, Sang Gu LEE
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Patent number: 11917820Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.Type: GrantFiled: July 6, 2021Date of Patent: February 27, 2024Assignee: SK hynix Inc.Inventors: Eun-Ho Kim, Eun-Joo Jung, Jong-Hyun Yoo, Ki-Jun Yun, Sung-Hoon Lee
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Publication number: 20240049464Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Inventors: Eun-Ho KIM, Eun-Joo JUNG, Jong-Hyun YOO, Ki-Jun YUN, Sung-Hoon LEE
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Patent number: 11462564Abstract: A method of manufacturing a semiconductor device includes forming a first etch stop pattern on a lower structure including a first region and a second region to expose the second region, stacking a plurality of stack structures on the lower structure to overlap the second region and the first etch stop pattern, forming a stepped stack structure by etching the plurality of stack structures to expose an end portion of the first etch stop pattern, forming a slit passing through the stepped stack structure and the first etch stop pattern, and replacing sacrificial layers of the plurality of stack structures and the first etch stop pattern with conductive patterns through the slit.Type: GrantFiled: October 21, 2020Date of Patent: October 4, 2022Assignee: SK hynix Inc.Inventors: In Su Park, Ki Jun Yun, Ki Hong Lee
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Publication number: 20210335800Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.Type: ApplicationFiled: July 6, 2021Publication date: October 28, 2021Inventors: Eun-Ho KIM, Eun-Joo JUNG, Jong-Hyun YOO, Ki-Jun YUN, Sung-Hoon LEE
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Patent number: 11088160Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.Type: GrantFiled: September 13, 2019Date of Patent: August 10, 2021Assignee: SK hynix Inc.Inventors: Eun-Ho Kim, Eun-Joo Jung, Jong-Hyun Yoo, Ki-Jun Yun, Sung-Hoon Lee
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Publication number: 20210036016Abstract: A method of manufacturing a semiconductor device includes forming a first etch stop pattern on a lower structure including a first region and a second region to expose the second region, stacking a plurality of stack structures on the lower structure to overlap the second region and the first etch stop pattern, forming a stepped stack structure by etching the plurality of stack structures to expose an end portion of the first etch stop pattern, forming a slit passing through the stepped stack structure and the first etch stop pattern, and replacing sacrificial layers of the plurality of stack structures and the first etch stop pattern with conductive patterns through the slit.Type: ApplicationFiled: October 21, 2020Publication date: February 4, 2021Applicant: SK hynix Inc.Inventors: In Su PARK, Ki Jun YUN, Ki Hong LEE
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Patent number: 10847536Abstract: A method of manufacturing a semiconductor device includes forming a first etch stop pattern on a lower structure including a first region and a second region to expose the second region, stacking a plurality of stack structures on the lower structure to overlap the second region and the first etch stop pattern, forming a stepped stack structure by etching the plurality of stack structures to expose an end portion of the first etch stop pattern, forming a slit passing through the stepped stack structure and the first etch stop pattern, and replacing sacrificial layers of the plurality of stack structures and the first etch stop pattern with conductive patterns through the slit.Type: GrantFiled: January 22, 2019Date of Patent: November 24, 2020Assignee: SK hynix Inc.Inventors: In Su Park, Ki Jun Yun, Ki Hong Lee
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Publication number: 20200295028Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.Type: ApplicationFiled: September 13, 2019Publication date: September 17, 2020Inventors: Eun-Ho KIM, Eun-Joo JUNG, Jong-Hyun YOO, Ki-Jun YUN, Sung-Hoon LEE
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Publication number: 20190378856Abstract: A method of manufacturing a semiconductor device includes forming a first etch stop pattern on a lower structure including a first region and a second region to expose the second region, stacking a plurality of stack structures on the lower structure to overlap the second region and the first etch stop pattern, forming a stepped stack structure by etching the plurality of stack structures to expose an end portion of the first etch stop pattern, forming a slit passing through the stepped stack structure and the first etch stop pattern, and replacing sacrificial layers of the plurality of stack structures and the first etch stop pattern with conductive patterns through the slit.Type: ApplicationFiled: January 22, 2019Publication date: December 12, 2019Applicant: SK hynix Inc.Inventors: In Su PARK, Ki Jun YUN, Ki Hong LEE
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Publication number: 20170200611Abstract: A manufacturing method for a memory device includes forming a stack structure over a substrate, forming a mask pattern over the stack structure, forming a first vertical hole by patterning the stack structure using the mask pattern, implanting a dopant into a sidewall of the first vertical hole to form a first region, wherein the first region is exposed by the mask pattern; and removing the first region to form a second vertical hole.Type: ApplicationFiled: June 14, 2016Publication date: July 13, 2017Inventors: In Su PARK, Ki Jun YUN, Ki Hong LEE
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Patent number: 9171783Abstract: A method for manufacturing a semiconductor device includes forming a lower electrode pattern on a substrate, forming a first insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first insulating layer, forming an etch blocking spacer at a side of the upper electrode pattern, forming a second insulating layer on the upper electrode pattern, etching the second insulating layer to form a cavity which exposes the etch blocking spacer, and forming a contact ball in the cavity.Type: GrantFiled: March 8, 2013Date of Patent: October 27, 2015Assignee: Dongbu Hitek Co., Ltd.Inventor: Ki Jun Yun
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Patent number: 9156681Abstract: Method for manufacturing a semiconductor device includes the steps of forming a lower electrode pattern on a substrate, forming a first interlayer insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first interlayer insulating layer, forming a second interlayer insulating layer on the upper electrode pattern, forming an etch blocking layer on a side of the upper electrode pattern, wherein the etch blocking layer passes through the first interlayer insulating layer, forming a cavity which exposes the side of the etch blocking layer by etching the second interlayer insulating layer, and forming a contact ball in the cavity.Type: GrantFiled: August 9, 2013Date of Patent: October 13, 2015Assignee: Dongbu HiTek Co., Ltd.Inventors: Chung Kyung Jung, Ki Jun Yun, Oh Jin Jung, Sang Wook Ryu, Seong Hun Jeong, Sung Wook Joo
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Patent number: 8697483Abstract: A method of forming a contact includes forming an inter-layer dielectric layer to cover a gate formed on a semiconductor substrate; and forming a first hole which passes through the inter-layer dielectric layer to expose the gate, a second hole which exposes an active region of the semiconductor substrate, and a third hole which exposes the semiconductor substrate at a preset depth. Further, the method includes forming a shielding layer on the semiconductor substrate including the bottom and sidewalls of the first hole, the second hole, and the third hole; and removing the shielding layer at the bottom of the first hole and the second hole to expose the gate and the active region. Furthermore, the method includes filling the first hole, the second hole, and the third hole with a conductive material.Type: GrantFiled: February 4, 2013Date of Patent: April 15, 2014Assignee: Dongbu HiTek Co., Ltd.Inventor: Ki Jun Yun
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Patent number: 8691610Abstract: A method of manufacturing a semiconductor device including at least one of the following steps: (1) Forming a plurality of lower electrodes over a substrate. (2) Forming a first stop film over the lower electrodes. (3) Forming a filling layer over the first stop film. (4) Forming a second stop film over the filling layer. (5) Forming a first interlayer insulating layer over the second stop film. (6) Forming a plurality of upper electrodes over the first interlayer insulating layer. (7) Forming a second interlayer insulating layer over the upper electrodes. (8) Etching the second interlayer insulating layer and the first interlayer insulating layer to form a cavity. (9) Forming a contact ball in the cavity.Type: GrantFiled: March 14, 2013Date of Patent: April 8, 2014Assignee: Dongbu HiTek Co., Ltd.Inventors: Seong Hun Jeong, Ki Jun Yun, Oh Jin Jung
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Publication number: 20140077371Abstract: A method of manufacturing a semiconductor device including at least one of the following steps: (1) Forming a plurality of lower electrodes over a substrate. (2) Forming a first stop film over the lower electrodes. (3) Forming a filling layer over the first stop film. (4) Forming a second stop film over the filling layer. (5) Forming a first interlayer insulating layer over the second stop film. (6) Forming a plurality of upper electrodes over the first interlayer insulating layer. (7) Forming a second interlayer insulating layer over the upper electrodes. (8) Etching the second interlayer insulating layer and the first interlayer insulating layer to form a cavity. (9) Forming a contact ball in the cavity.Type: ApplicationFiled: March 14, 2013Publication date: March 20, 2014Applicant: Dongbu HiTek Co., Ltd.Inventors: Seong Hun JEONG, Ki Jun YUN, Oh Jin JUNG
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Publication number: 20140070336Abstract: Method for manufacturing a semiconductor device includes the steps of forming a lower electrode pattern on a substrate, forming a first interlayer insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first interlayer insulating layer, forming a second interlayer insulating layer on the upper electrode pattern, forming an etch blocking layer on a side of the upper electrode pattern, wherein the etch blocking layer passes through the first interlayer insulating layer, forming a cavity which exposes the side of the etch blocking layer by etching the second interlayer insulating layer, and forming a contact ball in the cavity.Type: ApplicationFiled: August 9, 2013Publication date: March 13, 2014Applicant: DONGBU HITEK CO., LTD.Inventors: Chung Kyung JUNG, Ki Jun Yun, Oh Jin Jung, Sang Wook Ryu, Seong Hun Jeong, Sung Wook Joo
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Publication number: 20140070412Abstract: A method for manufacturing a semiconductor device includes forming a lower electrode pattern on a substrate, forming a first insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first insulating layer, forming an etch blocking spacer at a side of the upper electrode pattern, forming a second insulating layer on the upper electrode pattern, etching the second insulating layer to form a cavity which exposes the etch blocking spacer, and forming a contact ball in the cavity.Type: ApplicationFiled: March 8, 2013Publication date: March 13, 2014Inventor: Ki Jun YUN
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Patent number: 8664114Abstract: A method for fabricating an image sensor includes at least one of: (1) Forming a gate on a semiconductor substrate; (2) Forming spacers on both side walls of the gate and forming a dummy pattern on an upper portion of the semiconductor substrate; and (3) Forming a metal pad for an electrical connection on an upper portion of the dummy pattern. The method may include at least one of: (1) Forming an interlayer dielectric layer covering the entire semiconductor substrate, (2) Etching portions of the interlayer dielectric layer and the semiconductor substrate to form a super-contact hole; and (3) forming an insulation film on the entire surface of the interlayer dielectric layer. The method may include forming normal contact holes such that a portion of an upper portion of the gate and a partial region of the metal pad for an electrical connection are exposed and filling up the normal contact holes with a conductive material to form normal contacts.Type: GrantFiled: January 16, 2013Date of Patent: March 4, 2014Assignee: Dongbu HiTek Co., Ltd.Inventor: Ki-Jun Yun
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Publication number: 20130307035Abstract: A method for fabricating an image sensor includes at least one of: (1) Forming a gate on a semiconductor substrate; (2) Forming spacers on both side walls of the gate and forming a dummy pattern on an upper portion of the semiconductor substrate; and (3) Forming a metal pad for an electrical connection on an upper portion of the dummy pattern. The method may include at least one of: (1) Forming an interlayer dielectric layer covering the entire semiconductor substrate, (2) Etching portions of the interlayer dielectric layer and the semiconductor substrate to form a super-contact hole; and (3) forming an insulation film on the entire surface of the interlayer dielectric layer. The method may include forming normal contact holes such that a portion of an upper portion of the gate and a partial region of the metal pad for an electrical connection are exposed and filling up the normal contact holes with a conductive material to form normal contacts.Type: ApplicationFiled: January 16, 2013Publication date: November 21, 2013Applicant: DONGBU HITEK CO., LTD.Inventor: Ki-Jun YUN