Abstract: Provided are methods for programming in a non-volatile memory device, using incremental step pulses as a program voltage that is applied to a selected wordline. Methods may include applying a precharge voltage to an even bitline and an odd bitline such that the even bitline and the odd bitline are alternately charged with the precharge voltage and a boosted voltage that is higher than the precharge voltage. Methods may further include applying a bitline voltage corresponding to program data to a selected bitline of the even bitline and the odd bitline.

Abstract: A non-volatile memory device has multi-level cells (MLCs), which are programmed such that one page is written in the MLCs having previous states corresponding to at least one previous page. The non-volatile memory device includes a memory cell array, a row selection circuit and a page buffer block. The memory cell array includes the MLCs commonly coupled to a selected word line and respectively coupled to bitlines. The row selection circuit applies sequentially-decreasing read voltages to the selected wordline to read the previous states of the MLCs, and sequentially-decreasing verification voltages to the selected wordline to program states of the MLCs sequentially from a state having a highest threshold voltage to a state having a lowest threshold voltage. The page buffer block loads data corresponding to the one page, and controls a bitline voltage based on each previous state and each bit of the loaded data.

Abstract: A nonvolatile semiconductor memory includes a floating formation switch coupled to a bit line in a memory cell array. The floating formation switch maintains a channel voltage of memory cells coupled to the bit line at a level above a power supply voltage when the bit line is a non-selected bit line, which reduces electrical stress applied to the memory cells connected to the non-selected bit line during a read operation.

Abstract: Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.

Abstract: In a node structure under a capacitor in a ferroelectric random access memory device and a method of forming the same, top surfaces of the node structures are disposed at substantially the same level as a top surface of an interlayer insulating layer surrounding the node structures, and thus crystal growth of a ferroelectric in the capacitor can be stabilized. To this end, a node insulating pattern is formed on a semiconductor substrate. A node defining pattern surrounding the node insulating pattern is disposed under the node insulating pattern. A node conductive pattern is disposed between the node defining pattern and the node insulating pattern.

Abstract: A flash memory device comprises an array of memory cells capable of storing different numbers of bits per cell. A page buffer circuit for the flash memory device comprises a plurality of page buffers, each operating during programming, erasing, and reading operations of the memory cells. A control logic unit controls functions of the page buffers in accordance with the number of bits stored in corresponding memory cells.

Abstract: A phase change memory device and a method of fabricating the same are disclosed. The phase change memory device includes a first conductor pattern having a first conductivity type and a sidewall. A second conductor pattern is connected to the sidewall of the first conductor pattern to form a diode. A phase change layer is electrically connected to the second conductor pattern and a top electrode is connected to the phase change layer.

Abstract: A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

Abstract: In programming multi-pages in a flash memory device, a first page group and a second page group are formed with respect to each of at least one memory plane by grouping page buffers such that logical odd bitlines and logical even bitlines correspond to one of the first page group and the second page group, respectively. Program data corresponding to at least one page coupled to a selected wordline are loaded, and then a program voltage is applied to the selected wordline. A plurality of pages, including at least two pages pertaining to the same memory plane, can be simultaneously programmed and a row-coupling disturbance can be reduced.

Abstract: Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages.

Abstract: The present invention provides a flash memory device that comprises a word line; even page cells that are physically adjacent and connected to the word line; and odd page cells that are physically adjacent and connected to the word line, wherein at a program operation, page data is programmed in either one of the even page cells or the odd page cells.

Abstract: In one embodiment a semiconductor device includes odd contacts and respective odd lines. Spacers are formed on sidewalls of the odd lines and even openings for even lines are formed by performing an etching process. Even contacts are formed in the even openings and then even lines are formed.

Abstract: A non-volatile semiconductor memory device comprises first and second sub-memory arrays and a strapping line disposed between the first and second sub-memory arrays. A programming operation of the first sub-memory array is performed by simultaneously applying a programming voltage to odd and even bit lines connected to memory cells within the first sub-memory array.

Abstract: Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.

Abstract: A NAND flash memory device includes a plurality of stacked semiconductor layers, device isolation layer patterns disposed in predetermined regions of each of the plurality of semiconductor layers, the device isolation layers defining active regions, source and drain impurity regions in the active regions, a source line plug structure electrically connecting the source impurity regions, and a bit-line plug structure electrically connecting the drain impurity regions, wherein the source impurity regions are electrically connected to the semiconductor layers.

Abstract: Integrated circuit ferroelectric memory devices are provided that include an integrated circuit transistor. The memory device further includes a ferroelectric capacitor on the integrated circuit transistor. The ferroelectric capacitor includes a first electrode adjacent the transistor, a second electrode remote from the transistor and a ferroelectric film therebetween. The memory device further includes a plate line directly on the ferroelectric capacitor. Methods are also provided that include forming a ferroelectric capacitor on the integrated circuit transistor and forming a plate line directly on the ferroelectric capacitor.

Abstract: A flash memory device comprises a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.

Abstract: A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical shape, having its sidewalls conformally disposed on the lower inner walls of the opening. The filling insulation pattern fills an empty region surrounded by the sidewalls of the heating electrode. The phase change material pattern is disposed on the mold layer and downwardly extended to fill the empty part of the opening. The phase change material pattern contacts the top surfaces of the sidewalls of the heating electrode.

Abstract: A memory device may include L semiconductor layers, a gate structure on each of the semiconductor layers, N bitlines, and/or a common source line on each of the semiconductor layers. The L semiconductor layers may be stacked, and/or L may be an integer greater than 1. The N bitlines may be on the gate structures and crossing over the gate structures, and/or N may be an integer greater than 1. Each of the common source lines may be connected to each other such that the common source lines have equipotentiality with each other.

Abstract: A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of row and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes.