Patents by Inventor Ki-Nam Kim

Ki-Nam Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MULTI-BIT FLASH MEMORY DEVICE AND MEMORY CELL ARRAY
    Publication number: 20120039122
    Abstract: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.
    Type: Application
    Filed: October 24, 2011
    Publication date: February 16, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Tae PARK, Ki-Nam KIM, Yeong-Taek LEE
  • Semiconductor device and method of forming the same
    Publication number: 20110300683
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.
    Type: Application
    Filed: August 15, 2011
    Publication date: December 8, 2011
    Inventors: Jun-Beom Park, Soon-Moon Jung, Ki-Nam Kim
  • Multi-bit flash memory device and memory cell array
    Patent number: 8050089
    Abstract: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: November 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Ki-Nam Kim, Yeong-Taek Lee
  • APPARATUS AND METHOD FOR PREVENTING LAMP DAMAGE IN RAPID HEAT TREATMENT EQUIPMENT
    Publication number: 20110254451
    Abstract: Disclosed are an apparatus and method for preventing damage to the lamp of rapid heat treatment equipment. The most significant feature of the present invention is to provide an apparatus and method for preventing damage to a lamp in rapid heat treatment equipment, wherein the temperature of a quartz case comprising the lamp is sensed to identify an erratic increase in the temperature thereof so that problems with the lamp may be discovered early to take action. The apparatus and method according to the present invention allows the possibility of preventing damage or contamination of surrounding components due to lamp explosion; decisions regarding lamp replacement are also facilitated so that productivity can be enhanced. In addition, uniform lamp output may be ensured so that product quality is enhanced.
    Type: Application
    Filed: November 27, 2009
    Publication date: October 20, 2011
    Inventors: Sang Hyun Ji, Dae Gyou Jin, Ki Nam Kim
  • Semiconductor device and method of forming the same
    Patent number: 8026504
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: September 27, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Beom Park, Soon-Moon Jung, Ki-Nam Kim
  • TERMINAL ASSEMBLY FOR MOTOR OF HYBRID VEHICLE
    Publication number: 20110215662
    Abstract: The present invention features a terminal assembly for a motor of a hybrid vehicle as a wire connection structure of a concentrated winding motor, which can maintain a gap between a plurality of terminals using a clip and a holder in an insulated manner. Such a terminal assembly for a motor of a hybrid vehicle, includes: an open type holder with an open top; a plurality of terminals concentrically arranged and inserted into the holder; and a plurality of clips, each inserted between the terminals in an insulated manner to maintain a gap between the terminals.
    Type: Application
    Filed: November 19, 2010
    Publication date: September 8, 2011
    Applicants: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION, HYUNDAI MOBIS CO., LTD.
    Inventors: Hyeoun Dong Lee, Do Hyun Kim, Ki Nam Kim, Sam Gyun Kim, Tack Hwan Kwon
  • Headrest for vehicle
    Patent number: 7988234
    Abstract: The present invention discloses a headrest for a vehicle which is constructed in such a way that a headrest body 100 of the headrest 1 can be folded by releasing the locking state with a fixed member 70 fixed on the horizontal frame portion 12 of the mounting frame 10 using a catch 60 that is rotated in an interlocking state with rotation of a lever 50.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: August 2, 2011
    Assignee: Hyundai Motor Company
    Inventors: Ki Nam Kim, Hyun Ko, Hae Il Jeong
  • Flash memory devices that utilize age-based verify voltages to increase data reliability and methods of operating same
    Patent number: 7986560
    Abstract: Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: July 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Yong-Seok Kim, Ki-Nam Kim, Yeong-Taek Lee
  • MULTI-LAYER MEMORY DEVICES
    Publication number: 20110163411
    Abstract: A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.
    Type: Application
    Filed: March 16, 2011
    Publication date: July 7, 2011
    Inventors: Young-Chul Jang, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • Optical waveguide and coupler apparatus and method of manufacturing the same
    Publication number: 20110133063
    Abstract: Optical waveguide and coupler devices and methods include a trench formed in a bulk semiconductor substrate, for example, a bulk silicon substrate. A bottom cladding layer is formed in the trench, and a core region is formed on the bottom cladding layer. A reflective element, such as a distributed Bragg reflector can be formed under the coupler device and/or the waveguide device. Because the optical devices are integrated in a bulk substrate, they can be readily integrated with other devices on a chip or die in accordance with silicon photonics technology. Specifically, for example, the optical devices can be integrated in a DRAM memory circuit chip die.
    Type: Application
    Filed: October 25, 2010
    Publication date: June 9, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-chul Ji, Ki-nam Kim, Yong-woo Hyung, Kyoung-won Na, Kyoung-ho Ha, Yoon-dong Park, Dae-lok Bae, Jin-kwon Bok, Pil-kyu Kang, Sung-dong Suh, Seong-gu Kim, Dong-jae Shin, In-sung Joe
  • Methods of fabricating multi-layer nonvolatile memory devices
    Patent number: 7910433
    Abstract: A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: March 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Chul Jang, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • Phase change memory device
    Patent number: 7888667
    Abstract: A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical shape, having its sidewalls conformally disposed on the lower inner walls of the opening. The filling insulation pattern fills an empty region surrounded by the sidewalls of the heating electrode. The phase change material pattern is disposed on the mold layer and downwardly extended to fill the empty part of the opening. The phase change material pattern contacts the top surfaces of the sidewalls of the heating electrode.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Jong Song, Se-Ho Lee, Ki-Nam Kim, Su-Youn Lee, Jae-Hyun Park
  • Method of fabricating a MOS transistor with double sidewall spacers in a peripheral region and single sidewall spacers in a cell region
    Patent number: 7888198
    Abstract: An improved source/drain junction configuration in a metal-oxide semiconductor transistor is provided, as well as a novel method for fabricating this junction. This configuration employs gate double sidewall spacers in the peripheral region and gate single sidewall spacers in the cell array region. The double sidewall spacers are advantageously formed to suppress the short channel effect, to prevent current leakage, and to reduce sheet resistance. The insulating layer used to form the second spacers in the peripheral region remains in the cell array region and serves as an etching stopper during the etching step of interlayer insulating layer for contact opening formation and also serves as a barrier layer during the step of silicidation formation. As a result the fabrication process of the resulting device is simplified.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Suk Yang, Ki-Nam Kim, Chang-Hyun Cho
  • SEMICONDUCTOR DEVICES INCLUDING FIRST AND SECOND BIT LINES
    Publication number: 20110032763
    Abstract: In some embodiments, a semiconductor device includes first bit lines connected to respective first contacts. Spacers are disposed on sidewalls of the first bit lines. A second bit line is self-alignedly disposed between adjacent spacers, and a second contact is self-aligned with and connected to the second bit line.
    Type: Application
    Filed: October 21, 2010
    Publication date: February 10, 2011
    Inventors: Dong-Hwa Kwak, Jae-Kwan Park, Jae-Hwang Sim, Jin-Ho Kim, Ki-Nam Kim
  • Fe-based alloy having corrosion resistance and abrasion resistance and preparation method thereof
    Patent number: 7875134
    Abstract: A corrosion and wear resistant iron (Fe)-based alloy is provided. The Fe-based alloy consists essentially of 14.1 to 14.7% by weight of chromium (Cr), 1.41 to 1.47% by weight of carbon (C), 1.78 to 5.46% by weight of titanium (Ti), 0.11 to 0.39% by weight of aluminum (Al), 0.07 to 0.27% by weight of vanadium (V) and the balance of iron (Fe). The Fe-based alloy is highly resistant to corrosion and wear. In addition, since the Fe-based alloy is prepared using titanium alloy scrap at reduced cost, it is economically advantageous. Furthermore, the Fe-based alloy is environmentally friendly in terms of resource recycling. Further provided is a method for preparing the Fe-based alloy.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: January 25, 2011
    Assignee: IUCF-HYU (Industry-University Cooporation Foundation Hanyang University)
    Inventors: Seon Jin Kim, Gyung Guk Kim, Ji Hui Kim, Ki Nam Kim, Ji Young Kim
  • Methods of Forming One Transistor DRAM Devices
    Publication number: 20100330752
    Abstract: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.
    Type: Application
    Filed: July 23, 2010
    Publication date: December 30, 2010
    Inventors: Jae-Hun Jeong, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • Method for forming semiconductor device
    Patent number: 7842571
    Abstract: In one embodiment a semiconductor device includes odd contacts and respective odd lines. Spacers are formed on sidewalls of the odd lines and even openings for even lines are formed by performing an etching process. Even contacts are formed in the even openings and then even lines are formed.
    Type: Grant
    Filed: January 15, 2007
    Date of Patent: November 30, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hwa Kwak, Jae-Kwan Park, Jae-Hwang Sim, Jin-Ho Kim, Ki-Nam Kim
  • Non-volatile memory device and non-volatile semiconductor integrated circuit device, including the same
    Patent number: 7829929
    Abstract: A non-volatile memory device has improved operating characteristics. The non-volatile memory device includes an active region; a wordline formed on the active region to cross the active region; and a charge trapping layer interposed between the active region and the wordline, wherein a cross region of the active region and the wordline includes an overlap region in which the charge trapping layer is disposed and a non-overlap region in which the charge trapping layer is not disposed.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: November 9, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Seok Kang, Ki-Nam Kim
  • SEMICONDUCTOR DEVICES INCLUDING HYDROGEN IMPLANTATION LAYERS AND METHODS OF FORMING THE SAME
    Publication number: 20100240209
    Abstract: Provided are semiconductor devices and methods of forming the same. The semiconductor devices include a substrate further including a hydrogen implantation layer and a gate structure formed on the hydrogen implantation layer to include a first insulating layer, a charge storage layer, a second insulating layer and a conductive layer.
    Type: Application
    Filed: June 3, 2010
    Publication date: September 23, 2010
    Inventors: Jae-Hun Jeong, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • One transistor DRAM device and method of forming the same
    Patent number: 7795651
    Abstract: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: September 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hun Jeong, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang