Patents by Inventor Ki Soo Shin

Ki Soo Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020197817
    Abstract: The present invention discloses methods for forming a capacitor of a semiconductor device, including the steps of: forming a storage electrode conductive layer on a semiconductor substrate; coating a photoresist film on the storage electrode conductive layer; exposing the photoresist film to light according to an exposure process using a storage electrode phase shift mask, a boundary surface of a 0°-phase region and 180°-phase region of the phase shift mask being provided as a plane structure of the storage electrode; forming a storage electrode photoresist film pattern on the boundary surface by developing the exposed region; and etching the storage electrode conductive layer by using the photoresist film pattern as a mask, the storage electrode being formed by maintaining the storage electrode conductive layer in the plane structure of the storage electrode by generating a micro-loading effect.
    Type: Application
    Filed: May 6, 2002
    Publication date: December 26, 2002
    Applicant: Hynix Semiconductor Inc.
    Inventors: Cheol Kyu Bok, Ki Soo Shin
  • Publication number: 20020164541
    Abstract: Photoresist polymers, and photoresist compositions using the polymer are disclosed. More specifically, photoresist polymers containing maleimide represented by Formula 1. Photoresist compositions including the photoresist polymers have excellent etching resistance, heat resistance and adhesiveness, and development ability in aqueous tetramethylammonium hydroxide (TMAH) solution. As the compositions have low light absorbance at 193 nm and 157 nm wavelength, they are suitable for a process using ultraviolet light source such as VUV (157 nm).
    Type: Application
    Filed: March 27, 2002
    Publication date: November 7, 2002
    Inventors: Geun Su Lee, Jae Chang Jung, Ki Soo Shin
  • Publication number: 20020128410
    Abstract: An organic anti-reflective polymer which prevents back reflection of lower film layers and eliminates standing wave that is occurred by a thickness change of photoresist and light, in a process for fabricating ultrafine patterns that use photoresist for lithography by using 193 nm ArF and its preparation method. More particularly, the organic anti-reflective polymer of the present invention is useful for fabricating ultrafine patterns of 64M, 256M, 1G, and 4G DRAM semiconductor devices. A composition containing such organic anti-reflective polymer, an anti-reflective coating layer made therefrom and a preparation method thereof.
    Type: Application
    Filed: January 4, 2002
    Publication date: September 12, 2002
    Inventors: Min-Ho Jung, Jae-Chang Jung, Geun-Su Lee, Ki-Soo Shin
  • Publication number: 20020081504
    Abstract: A pattern width slimming-inhibiting method of photoresist pattern using photoresist composition containing thermal acid generator. When the formed pattern is heated, a thermal generator generates acid during the heating process, and a cross-linking reaction occurs to photoresist compositions, thereby preventing pattern width slimming due to SEM-beam for CD measurement.
    Type: Application
    Filed: December 5, 2001
    Publication date: June 27, 2002
    Inventors: Keun Kyu Kong, Gyu Dong Park, Jae Chang Jung, Ki Soo Shin
  • Patent number: 5710735
    Abstract: An EEPROM including a selecting gate which overlaps with one side of a floating gate and a certain part of a source electrode and a control gate which overlaps with the other side of the floating gate and a certain part of a drain electrode, is improved in charge coupling ratio, showing an increase in program efficiency even at low outer voltages. Application of low outer voltages to the EEPROM brings about a decrease in both the breakdown voltage and the junction breakdown voltage of the gate oxide film of peripheral transistors, allowing a shallow junction and a thin gate oxide film process to be possible. A shallow junction can be effected by an ion-implanting process which results in formation of a source electrode and a drain electrode.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: January 20, 1998
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Ki Soo Shin, Soo Han Choi