Patents by Inventor Ki-Youn Jang

Ki-Youn Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8519517
    Abstract: A semiconductor package system, and method of manufacturing thereof, includes: an electrical substrate having a contact pad; a support structure having a lead finger thereon; a bump on the lead finger, the bump clamped on a top and a side of the lead finger and connected with the contact pad; and an encapsulant over the lead finger and the electrical substrate.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: August 27, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Hun Teak Lee, Jong Kook Kim, ChulSik Kim, Ki Youn Jang
  • Patent number: 8513057
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a routable layer having a column; mounting an integrated circuit structure in direct contact with the column; and forming a gamma connector to electrically connect the column to the integrated circuit structure.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: August 20, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Oh Han Kim, Ki Youn Jang, DaeSik Choi, DongSoo Moon
  • Patent number: 8471394
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated circuit package including: providing a base substrate, connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon, mounting a base component over the base substrate, and forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system; and releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: June 25, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Ki Youn Jang, HeeJo Chi, NamJu Cho
  • Publication number: 20130154121
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate, the integrated circuit having an inactive side and a non-horizontal side; mounting a mold chase having a buffer layer over the integrated circuit; forming an encapsulation between the substrate and the buffer; and removing the mold chase, leaving the encapsulation having a recess exposing a portion of the non-horizontal side.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Inventors: JaeHyun Lee, Ki Youn Jang, DokOk Yu
  • Publication number: 20130069224
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a routable layer having a column; mounting an integrated circuit structure in direct contact with the column; and forming a gamma connector to electrically connect the column to the integrated circuit structure.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Inventors: Oh Han Kim, Ki Youn Jang, DaeSik Choi, DongSoo Moon
  • Patent number: 8368200
    Abstract: A method of manufacture of a shielded stacked integrated circuit packaging system includes: forming a first integrated circuit structure having a first substrate and a first integrated circuit die; mounting a shield over the first substrate and the first integrated circuit die; mounting a second integrated circuit structure having a second substrate and a second integrated circuit die over the shield; and forming a package encapsulation for covering the first integrated circuit die, the shield, and the second integrated circuit structure.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: February 5, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Ki Youn Jang, YoungMin Kim, Hyung Jun Jeon
  • Patent number: 8304900
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit device to the substrate; forming a stud interconnect having stacked studs, the stud interconnect on the substrate and having a contact surface and a crown surface on an end of the stud interconnect opposite the substrate; applying an encapsulation over the integrated circuit die, over the stud interconnect, and over the substrate; and forming a cavity in the encapsulation over the stud interconnect, the contact surface and the crown surface exposed in the cavity.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Ki Youn Jang, YoungJoon Kim, JoHyun Bae
  • Publication number: 20120267801
    Abstract: An integrated circuit package system that includes: a support structure including an electrical contact; a solder mask over the support structure, the solder mask including a solder mask flange, the solder mask flange directly on a support structure first surface; an integrated circuit over the support structure; and encapsulant over the integrated circuit and in contact with the solder mask flange. A mold system that includes a first mold having a projection along a first mold bottom surface, the projection between a first cavity and a recess.
    Type: Application
    Filed: June 28, 2012
    Publication date: October 25, 2012
    Inventors: Ki Youn Jang, Sungmin Song, JoHyun Bae
  • Patent number: 8256660
    Abstract: A semiconductor package system, and method of manufacturing thereof, includes: a die having a contact pad; a lead finger having a substantially trapezoidal cross-section; a bump clamped on a top and a side of the lead finger, the bump connected to the contact pad; and an encapsulant over the lead finger and the die, the encapsulant with a bottom of the lead finger exposed.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: September 4, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Hun Teak Lee, Jong Kook Kim, ChulSik Kim, Ki Youn Jang
  • Patent number: 8252615
    Abstract: An integrated circuit package system that includes: providing a support structure including an integrated circuit and an electrical contact adjacent thereto; providing a first mold having a first cavity with a projection and a recess for collecting flash; engaging the first mold on the support structure with the first cavity over at least a portion of the integrated circuit and the projection and the recess between the at least a portion of the integrated circuit and the electrical contact; and injecting encapsulation material into the first cavity.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: August 28, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Ki Youn Jang, Sungmin Song, JoHyun Bae
  • Publication number: 20120193132
    Abstract: An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.
    Type: Application
    Filed: April 6, 2012
    Publication date: August 2, 2012
    Inventors: Haengcheol Choi, Ki Youn Jang, Taewoo Kang, Il Kwon Shim
  • Publication number: 20120119360
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 17, 2012
    Inventors: YoungChul Kim, KyungHoon Lee, Seong Won Park, Ki Youn Jang, JaeHyun Lee, DeokKyung Yang, In Sang Yoon, SungEun Park
  • Patent number: 8178392
    Abstract: An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: May 15, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Haengcheol Choi, Ki Youn Jang, Taewoo Kang, Il Kwon Shim
  • Patent number: 8129263
    Abstract: A method of manufacture of a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, the semiconductor die having a die pad; mounting a lead finger on the substrate; attaching a support pedestal on sides of the lead finger; and attaching a wire interconnection between the die pad and the support pedestal, the wire interconnection having a ball bond on the die pad and a stitch bond on the support pedestal.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: March 6, 2012
    Assignee: Chippac, Inc.
    Inventors: Hun-Teak Lee, Jong-Kook Kim, Chul-Sik Kim, Ki-Youn Jang, Rajendra D. Pendse
  • Publication number: 20120038040
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit device to the substrate; forming a stud interconnect having stacked studs, the stud interconnect on the substrate and having a contact surface and a crown surface on an end of the stud interconnect opposite the substrate; applying an encapsulation over the integrated circuit die, over the stud interconnect, and over the substrate; and forming a cavity in the encapsulation over the stud interconnect, the contact surface and the crown surface exposed in the cavity.
    Type: Application
    Filed: August 11, 2010
    Publication date: February 16, 2012
    Inventors: Ki Youn Jang, YoungJoon Kim, JoHyun Bae
  • Patent number: 8110908
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate cavity; mounting a bottom flip chip die below the substrate; mounting an internal integrated circuit die above the substrate; filling between the internal integrated circuit die and the substrate and between the bottom flip chip die and the substrate with a substance filling through the substrate cavity; and encapsulating the internal integrated circuit die with an encapsulation.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: February 7, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: YoungJoon Kim, Ki Youn Jang
  • Publication number: 20120025398
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated circuit package including: providing a base substrate, connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon, mounting a base component over the base substrate, and forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system; and releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed.
    Type: Application
    Filed: October 7, 2011
    Publication date: February 2, 2012
    Inventors: Ki Youn Jang, HeeJo Chi, NamJu Cho
  • Publication number: 20110298107
    Abstract: A method of manufacture of a shielded stacked integrated circuit packaging system includes: forming a first integrated circuit structure having a first substrate and a first integrated circuit die; mounting a shield over the first substrate and the first integrated circuit die; mounting a second integrated circuit structure having a second substrate and a second integrated circuit die over the shield; and forming a package encapsulation for covering the first integrated circuit die, the shield, and the second integrated circuit structure.
    Type: Application
    Filed: August 17, 2011
    Publication date: December 8, 2011
    Inventors: Ki Youn Jang, YoungMin Kim, Hyung Jun Jeon
  • Publication number: 20110285000
    Abstract: A semiconductor package system, and method of manufacturing thereof, includes: an electrical substrate having a contact pad; a support structure having a lead finger thereon; a bump on the lead finger, the bump clamped on a top and a side of the lead finger and connected with the contact pad; and an encapsulant over the lead finger and the electrical substrate.
    Type: Application
    Filed: July 29, 2011
    Publication date: November 24, 2011
    Inventors: Hun Teak Lee, Jong Kook Kim, ChulSik Kim, Ki Youn Jang
  • Publication number: 20110266700
    Abstract: A method of manufacture of a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, the semiconductor die having a die pad; mounting a lead finger on the substrate; attaching a support pedestal on sides of the lead finger; and attaching a wire interconnection between the die pad and the support pedestal, the wire interconnection having a ball bond on the die pad and a stitch bond on the support pedestal.
    Type: Application
    Filed: July 7, 2011
    Publication date: November 3, 2011
    Inventors: Hun-Teak Lee, Jong-Kook Kim, Chul-Sik Kim, Ki-Youn Jang, Rajendra D. Pendse