Abstract: A powergating circuit includes a P-channel transistor with a source coupled to VCC, a gate for receiving a first boosted or non-boosted powergating control signal, and a drain forming the internal switched VCC power supply. An N-channel transistor has a source coupled to VSS, a gate for receiving a second boosted or non-boosted powergating control signal, and a drain forming the internal switched VSS power supply. The powergating circuit further includes a circuit for forcing the first and second internal power supply voltages to a mid-point reference voltage during the standby mode.

Abstract: A precharge initiated dynamic random access memory (DRAM) technique of especial utility with respect to DRAM devices and other integrated circuit devices incorporating embedded DRAM in which the rising edge of each clock initiates a precharge to those subarrays that were active as opposed to conventional techniques wherein the subarrays are typically precharged so that they are made ready on the rising edge of the clock, which would then start an active cycle. The longer restore time that is achieved can be used to enable the establishment of better logic “1” and “0” levels in the memory cells, to reduce the device clock period and/or to enable other functions to be performed in parallel with the precharge function.

Abstract: Power consumption in an integrated circuit memory is reduced by lowering the power supply demand from an on-chip pumped VCCP power source. Only the row decoders for subarrays in a memory bank that were previously activated are precharged in response to a bank precharge command. Additional circuitry is provided to the precharge clock generator circuit. The additional circuitry includes a latch that is set when an array select signal is asserted, and reset when a precharge operation for that bank occurs.

Abstract: A powergating circuit includes an MOS circuit such as a memory circuit having a first power terminal and a second power terminal, a P-channel transistor having a drain coupled to the first power terminal of the MOS circuit, and an N-channel transistor having a drain coupled to the second power terminal of the MOS circuit. In order to minimize leakage current and resultant power dissipation a negative VGS voltage is established in the transistors during a standby mode and a boosted VGS voltage is established in the transistors during an active mode.

Abstract: A column read amplifier power-gating technique for DRAM devices and those devices incorporating embedded DRAM which incorporate a power-down (or Sleep) mode of operation which overcomes the deficiencies of conventional power-gating approaches by eliminating the need for a large, separate power-gating transistor thereby saving on-chip area yet still reducing power during Sleep Mode. In operation, the column select signal YR is controlled such that it is driven below VSS during Sleep Mode when N-channel pass transistors are used in the column read amplifier or to a supply voltage level of VCC when P-channel devices are used instead. This significantly reduces the current through the pass transistors and yet causes no reduction in the switching speed of the column read amplifiers.

Abstract: A refresh circuit is used for refreshing or masking from refresh non-contiguous subarrays in an integrated circuit memory array. At the initiation of each masked refresh cycle the address inputs, which normally are ignored, are evaluated to indicate which subarrays should be refreshed and which should be not refreshed. Power is saved due to the flexibility in determining which subarrays are refreshed at each new refresh cycle.

Abstract: A refresh circuit is used for refreshing or masking from refresh non-contiguous subarrays in an integrated circuit memory array. At the initiation of each masked refresh cycle the address inputs, which normally are ignored, are evaluated to indicate which subarrays should be refreshed and which should be not refreshed. Power is saved due to the flexibility in determining which subarrays are refreshed at each new refresh cycle.

Abstract: A bitline reference voltage circuit according to the present invention includes a first transistor having a current path coupled between a first bitline and an intermediate node, and a gate for receiving a first control signal, a second transistor having a current path coupled between a second bitline and the intermediate node, and a gate for receiving a second control signal, a third transistor having current path coupled between the intermediate node and a source of constant voltage, and a gate for receiving a third control signal, and a capacitor coupled between the intermediate node and the source of constant voltage.

Abstract: A bitline reference voltage circuit according to the present invention includes a first transistor having a current path coupled between a first bitline and an intermediate node, and a gate for receiving a first control signal, a second transistor having a current path coupled between a second bitline and the intermediate node, and a gate for receiving a second control signal, a third transistor having current path coupled between the intermediate node and a source of constant voltage, and a gate for receiving a third control signal, and a capacitor coupled between the intermediate node and the source of constant voltage.

Abstract: A powergating circuit includes an MOS circuit such as a memory circuit having a first power terminal and a second power terminal, a P-channel transistor having a drain coupled to the first power terminal of the MOS circuit, and an N-channel transistor having a drain coupled to the second power terminal of the MOS circuit. In order to minimize leakage current and resultant power dissipation a negative VGS voltage is established in the transistors during a standby mode and a boosted VGS voltage is established in the transistors during an active mode.

Abstract: An optimized read data amplifier for the output data path of integrated circuit memory arrays comprises a fast, low power and small on-chip area consuming circuit which is advantageously effectuated through the combined application of “current sensing” and “voltage sensing” techniques. In a particular embodiment disclosed herein, an amplifier enable signal is timed with the column read address so that the amplifier is turned “off” when not in use and both data read lines (“DR” and “DRB”) are precharged “high”. No clocking of the read data amplifier is required in order to obviate undesired clock latencies and pipelining and a simple mechanism is implemented such that control of power-up and power-down results in further power savings.

Abstract: A high voltage transistor protection technique and switching circuit of especial applicability to integrated circuit devices utilizing multiple power supply voltages. In accordance with the technique of the present intention, the problems inherent in the amount of on-chip die area consumed and speed degradation of prior art circuit implementations are overcome by furnishing a substantially direct current voltage VHVP to the gate of a first transistor of a series connected thin gate oxide pair wherein VHVP≦VDSMAX (the maximum gate-to-source voltage of the first transistor) and VHVP≦VDSMAX+Vt (the maximum drain-to-source voltage of the second transistor plus the threshold voltage of the first transistor).

Abstract: A circuit and method for an integrated circuit memory incorporates a look-ahead function where refresh commands are presented to the device at least one cycle before actual internal refresh operations occur. Active cycles are executed on the same clock as the external command is applied. Active commands are unaltered and are executed on the same clock cycle as the occurrence of the active command. Active commands can be executed immediately without waiting to determine if the row address latch is to be sourced externally or internally.

Abstract: A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.

Abstract: A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.

Abstract: A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.

Abstract: A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.

Abstract: A circuit and method for an integrated circuit memory incorporates a look-ahead function where refresh commands are presented to the device at least one cycle before actual internal refresh operations occur. Active cycles are executed on the same clock as the external command is applied. Active commands are unaltered and are executed on the same clock cycle as the occurrence of the active command. Active commands can be executed immediately without waiting to determine if the row address latch is to be sourced externally or internally.

Abstract: An automatic delay technique for early “read” and “write” memory access operations in synchronous dynamic random access memory (“SDRAM”) devices and those integrated circuit devices employing embedded SDRAM arrays. A circuit and method is provided which controls the internal column select (“Yi”) and data signals such that the column address strobe (“/CAS”) signal is allowed to go “active” in advance of that otherwise possible in conjunction with conventional SDRAM arrays. In an exemplary embodiment, the column select signals (“read” or “write”) are delayed until either the corresponding, pre-decoded column address signal or the respective column clock signal is valid, whichever occurs later.

Abstract: A voltage down converter with hysteresis generator combining a hysteresis signal to a reference voltage and an output voltage feedback signal applied to a comparator. The hysteresis generator is coupled to a control signal giving advance notice of when a high current load is to be activated. The hysteresis signal is switched to a first state prior to the high current load activation, and switched to a second state after the high current load activation. In the first state, the hysteresis voltage is added to a reference voltage. In the second state, the hysteresis voltage is added to the voltage output feedback signal.